Abstract: A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous line level low-k dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous line level low-k dielectric; a second thin non-porous via level low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

Abstract: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.

Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05?v?0.8, 0?w?0.9, 0.05?x?0.8, 0?y?0.3, 0.05?z?0.08 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

Abstract: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.

Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

Abstract: Disclosed is a MOSFET structure and method of fabricating the structure that incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. In one embodiment, the multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. In another embodiment, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. Either embodiment may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.

Abstract: An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

Abstract: A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

Abstract: A process for fabricating a low dielectric constant semiconductor comprising the steps of: depositing a first metal layer on a substrate; patterning the first metal layer to produce a patterned first metal wiring; applying a first insulating material onto the patterned first metal wiring to form a support structure; patterning the first insulating material by a contact printing process; depositing a second insulating material of lower dielectric constant onto the support structure; planarizing the second insulating material; depositing a polish-stop film layer over the planarized second insulating material, thereby forming a plurality of metal studs; depositing a second metal layer onto the polish-stop film layer forming interconnects with said studs; and patterning the metal layer to produce a second metal wiring interconnecting to the first wiring via the metal studs.

Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

Abstract: A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

Abstract: An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.