Patents by Inventor Chul Hong Park
Chul Hong Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10720429Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.Type: GrantFiled: April 22, 2019Date of Patent: July 21, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Deepak Sharma, Hyun-jong Lee, Raheel Azmat, Chul-hong Park, Sang-jun Park
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Patent number: 10707163Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.Type: GrantFiled: November 27, 2018Date of Patent: July 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Vincent Chun Fai Lau, Jung-ho Do, Byung-sung Kim, Chul-hong Park
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Patent number: 10699052Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.Type: GrantFiled: August 1, 2019Date of Patent: June 30, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chul-Hong Park, Su-Hyeon Kim, Sharma Deepak
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Publication number: 20200057830Abstract: An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.Type: ApplicationFiled: May 2, 2019Publication date: February 20, 2020Inventors: Raheel Azmat, Sidharth Rastogi, Chul-hong Park, Jae-seok Yang, Kwan-young Chun
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Patent number: 10546855Abstract: Integrated circuit devices are provided. The IC devices may include an active region extending in a first direction, first and second gate electrodes extending in a second direction, a first impurity region in the active region adjacent a first side of the first gate electrode, a second impurity region in the active region between a second side of the first gate electrode and a first side of the second gate electrode, a third impurity region in the active region adjacent a second side of the second gate electrode, a cross gate contact electrically connecting the first and second impurity regions, a first contact electrically connected to the third impurity region, a first wire electrically connected to the cross gate contact, and a second wire electrically connected to the first contact. The first and second wires may extend only in the first direction and may be on the same line.Type: GrantFiled: March 30, 2017Date of Patent: January 28, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Rajeev Ranjan, Deepak Sharma, Subhash Kuchanuri, Chul Hong Park, Jae Seok Yang, Kwan Young Chun
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Patent number: 10497645Abstract: A semiconductor device includes a first conductive element, a first insulating layer and a second insulating layer sequentially disposed on the first conductive element, a conductive via passing through the first insulating layer and the second insulating layer. The conductive via is connected to the first conductive element. The semiconductor device includes a via extension portion disposed in the second insulating layer that extends along an upper surface of the first insulating layer from one side surface of the conductive via, and a second conductive element disposed on the second insulating layer that is connected to the via extension portion.Type: GrantFiled: January 10, 2019Date of Patent: December 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Yubo Qian, Byung Sung Kim, Hyeon Uk Kim, Young Gook Park, Chul Hong Park
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Publication number: 20190354655Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.Type: ApplicationFiled: August 1, 2019Publication date: November 21, 2019Inventors: Chul-Hong Park, Su-Hyeon Kim, Sharma Deepak
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Publication number: 20190355719Abstract: A semiconductor device includes first to fourth cells sequentially disposed on a substrate, first to third diffusion break structures, a first fin structure configured to protrude from the substrate, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion break structures, a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure, the second fin structure comprising fifth to eighth fins separated from each other by the first to third diffusion break structures, the first to fourth gate electrodes being disposed in the first to fourth cells, respectively, and the number of fins in one cell of the first to fourth cells is different from the number of fins in an other cell of the first to fourth cells.Type: ApplicationFiled: April 1, 2019Publication date: November 21, 2019Inventors: Shigenobu MAEDA, Sung Chul PARK, Chul Hong PARK, Yoshinao HARADA, Sung Min KANG, Ji Wook KWON, Ha-Young KIM, Yuichi HIRANO
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Patent number: 10474783Abstract: A method of designing a layout of a semiconductor device includes designing layouts of cells, each layout including first conductive lines, the first conductive lines extending in a first direction and being spaced apart from each other in a second direction crossing the first direction, disposing the layouts of the cells to be adjacent to each other in the first direction, such that the first conductive lines in adjacent layouts of the cells are connected to each other, and disposing insulation blocks at a boundary area between adjacent ones of the layouts of the cells or in areas of the layouts of the cells adjacent to the boundary area, such that the insulation blocks block connections between some of the first conductive lines.Type: GrantFiled: September 12, 2017Date of Patent: November 12, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sidharth Rastogi, Subhash Kuchanuri, Chul-Hong Park, Jae-Seok Yang
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Publication number: 20190326285Abstract: An integrated circuit device includes a substrate including a fin active region extending in a first direction, a gate line intersecting the fin active region and extending in a second direction perpendicular to the first direction, a power line electrically connected to source/drain regions at sides of the gate line on the fin active region, a pair of dummy gate lines intersecting the fin active region and extending in the second direction, and a device separation structure electrically connected to the pair of dummy gate lines and including a lower dummy contact plug between the pair of dummy gate lines on the fin active region and electrically connected to the power line, and an upper dummy contact plug on the lower dummy contact plug and on the pair of dummy gate lines to electrically connect the lower dummy contact plug to the pair of dummy gate lines.Type: ApplicationFiled: June 26, 2019Publication date: October 24, 2019Inventors: Sidharth RASTOGI, Subhash KUCHANURI, Raheel AZMAT, Pan-jae PARK, Chul-hong PARK, Jae-seok YANG, Kwan-young CHUN
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Patent number: 10402528Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.Type: GrantFiled: December 11, 2015Date of Patent: September 3, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chul-Hong Park, Su-Hyeon Kim, Sharma Deepak
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Patent number: 10403619Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes first and second logic cells adjacent to each other in a first direction on a substrate, a gate electrode extending in the first direction in each of the first and second logic cells, a power line extending in a second direction at a boundary between the first and second logic cells, and a connection structure electrically connecting the power line to an active pattern of the first logic cell and to an active pattern of the second logic cell. The connection structure lies below the power line and extends from the first logic cell to the second logic cell. A top surface of the connection structure is at a higher level than that of a top surface of the gate electrode.Type: GrantFiled: October 18, 2017Date of Patent: September 3, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yubo Qian, Byung-Sung Kim, Chul-Hong Park, Haewang Lee
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Publication number: 20190252380Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.Type: ApplicationFiled: April 22, 2019Publication date: August 15, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Deepak SHARMA, Hyun-jong Lee, Raheel Azmat, Chul-hong Park, Sang-jun Park
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Patent number: 10361198Abstract: An integrated circuit device includes a substrate including a fin active region extending in a first direction, a gate line intersecting the fin active region and extending in a second direction perpendicular to the first direction, a power line electrically connected to source/drain regions at sides of the gate line on the fin active region, a pair of dummy gate lines intersecting the fin active region and extending in the second direction, and a device separation structure electrically connected to the pair of dummy gate lines and including a lower dummy contact plug between the pair of dummy gate lines on the fin active region and electrically connected to the power line, and an upper dummy contact plug on the lower dummy contact plug and on the pair of dummy gate lines to electrically connect the lower dummy contact plug to the pair of dummy gate lines.Type: GrantFiled: May 24, 2017Date of Patent: July 23, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sidharth Rastogi, Subhash Kuchanuri, Raheel Azmat, Pan-jae Park, Chul-hong Park, Jae-seok Yang, Kwan-young Chun
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Publication number: 20190221563Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.Type: ApplicationFiled: March 25, 2019Publication date: July 18, 2019Inventors: Jung-hyuck CHOI, Hae-wang LEE, Hyoun-jee HA, Chul-hong PARK
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Patent number: 10319720Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.Type: GrantFiled: December 20, 2017Date of Patent: June 11, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-hyuck Choi, Hae-wang Lee, Hyoun-jee Ha, Chul-hong Park
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Patent number: 10297596Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.Type: GrantFiled: April 25, 2017Date of Patent: May 21, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Deepak Sharma, Hyun-jong Lee, Raheel Azmat, Chul-hong Park, Sang-jun Park
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Publication number: 20190148292Abstract: A semiconductor device includes a first conductive element, a first insulating layer and a second insulating layer sequentially disposed on the first conductive element, a conductive via passing through the first insulating layer and the second insulating layer. The conductive via is connected to the first conductive element. The semiconductor device includes a via extension portion disposed in the second insulating layer that extends along an upper surface of the first insulating layer from one side surface of the conductive via, and a second conductive element disposed on the second insulating layer that is connected to the via extension portion.Type: ApplicationFiled: January 10, 2019Publication date: May 16, 2019Inventors: Yubo Qian, Byung Sung Kim, Hyeon Uk Kim, Young Gook Park, Chul Hong Park
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Publication number: 20190122988Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.Type: ApplicationFiled: December 12, 2018Publication date: April 25, 2019Inventors: Hyo-Jin KIM, Chang-Hwa KIM, Hwi-Chan JUN, Chul-Hong PARK, Jae-Seok YANG, Kwan-Young CHUN
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Publication number: 20190109088Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.Type: ApplicationFiled: November 27, 2018Publication date: April 11, 2019Inventors: Vincent Chun Fai LAU, Jung-ho DO, Byung-sung KIM, Chul-hong PARK