Patents by Inventor Chul-Moon JUNG
Chul-Moon JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960755Abstract: A semiconductor memory device comprises: first storage logic configured to store, as first addresses, ‘K’ addresses having different values among input addresses applied during the enable period of a reference signal, second storage logic configured to store, as second addresses, ‘L’ addresses corresponding to a time point at which the enable period of the reference signal is ended among the input addresses, an order controller configured to determine a first output order of each of the first addresses based on a number of times each of the first addresses is repeatedly input, and to determine a second output order for outputting mixed addresses obtained by mixing the first addresses based on the first output order and the second addresses together, and refresh operation logic configured to apply the mixed addresses according to the second output order, to a target refresh operation.Type: GrantFiled: December 13, 2021Date of Patent: April 16, 2024Assignee: SK hynix Inc.Inventors: Woongrae Kim, Kwi Dong Kim, Chul Moon Jung, Jeong Tae Hwang
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Publication number: 20240104209Abstract: A memory device includes a memory cell region including a plurality of rows; a row-hammer control circuit including first and second queues, and configured to: read counting data from a row indicated by a row address according to an active command, store the row address in the first queue according to a comparison result of the counting data and a first set value, store the row address in the second queue according to a comparison result of the counting data and a second set value, and select, as a row-hammer address according to a refresh management command or a target refresh command, one of the row addresses stored in the first queue and the second queue; and a row control circuit configured to refresh one or more rows corresponding to the row-hammer address according to the refresh management command or the target refresh command.Type: ApplicationFiled: August 22, 2023Publication date: March 28, 2024Inventors: Jeong Jin HWANG, Chul Moon JUNG
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Patent number: 11928362Abstract: A fuse latch of a semiconductor device including PMOS transistors and NMOS transistors includes a data transmission circuit configured to transmit data to a first node and a second node in response to a first control signal, a latch circuit configured to latch the data received from the data transmission circuit through the first node and the second node, and a data output circuit configured to output the data latched by the latch circuit in response to a second control signal. NMOS transistors contained in the data transmission circuit, the latch circuit, and the data output circuit may be formed in first, fourth, and fifth active regions, PMOS transistors are formed in second and third active regions, and the first to fifth active regions are sequentially arranged in a first direction.Type: GrantFiled: December 20, 2021Date of Patent: March 12, 2024Assignee: SK hynix inc.Inventors: Jae Hwan Seo, Chul Moon Jung
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Publication number: 20240046977Abstract: An integrated circuit includes: first and second pattern generation circuits generating first and second pattern signal for a sampling section; a first section control part generating a coarse section signal for a first section of the sampling section, according to the first pattern signal; a first filter part generating a first section extract signal by filtering the second pattern signal according to the coarse section signal; a second section control part generating a fine section signal for a second section of the sampling section, according to the first section extract signal; a second filter part generating a second section extract signal by filtering the second pattern signal according to the fine section signal; an output control circuit generating a sampling enable signal according to the first and second section extract signals; and a sampling circuit suitable for sampling an input signal according to the sampling enable signal.Type: ApplicationFiled: October 17, 2023Publication date: February 8, 2024Inventors: Woongrae KIM, Byeong Yong GO, Chul Moon JUNG, Yoonna OH
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Patent number: 11823730Abstract: An integrated circuit includes: first and second pattern generation circuits generating first and second pattern signal for a sampling section; a first section control part generating a coarse section signal for a first section of the sampling section, according to the first pattern signal; a first filter part generating a first section extract signal by filtering the second pattern signal according to the coarse section signal; a second section control part generating a fine section signal for a second section of the sampling section, according to the first section extract signal; a second filter part generating a second section extract signal by filtering the second pattern signal according to the fine section signal; an output control circuit generating a sampling enable signal according to the first and second section extract signals; and a sampling circuit suitable for sampling an input signal according to the sampling enable signal.Type: GrantFiled: March 24, 2022Date of Patent: November 21, 2023Assignee: SK hynix Inc.Inventors: Woongrae Kim, Byeong Yong Go, Chul Moon Jung, Yoonna Oh
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Publication number: 20230335175Abstract: A method for operating a memory includes: receiving an active command and a row address; confirming that a portion of columns of a first row corresponding to the row address is replaced with a portion of columns of a second row; activating the first row and the second row; confirming activation of a random pulse; randomly selecting one among the row address corresponding to the first row and a row address corresponding to the second row in response to the activation of the random pulse; and sampling the selected row address as a sampling address.Type: ApplicationFiled: August 31, 2022Publication date: October 19, 2023Inventors: Woongrae KIM, Yoonna OH, Chul Moon JUNG
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Publication number: 20230298653Abstract: An operation method of a memory may include entering a self-refresh mode, increasing a level of a back-bias voltage in response to entering the self-refresh mode, performing self-refresh operations in a first cycle, confirming that the back-bias voltage reaches a level of a first threshold voltage, and performing the self-refresh operations in a second cycle longer than the first cycle in response to the confirmation.Type: ApplicationFiled: November 4, 2022Publication date: September 21, 2023Inventors: Woongrae KIM, Chul Moon JUNG
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Publication number: 20230215484Abstract: A semiconductor memory device includes: a memory cell region including a plurality of cell mats in each of which a plurality of rows are disposed, each row coupled to normal cells and row-hammer cells; a repair control circuit suitable for generating a pairing flag denoting whether a cell mat in which an active row corresponding to an active address is disposed, is repaired with another cell mat; and a refresh control circuit suitable for: selecting, when an active command is inputted, a sampling address based on first and second data read from the row-hammer cells of the active row, refreshing, when a target refresh command is inputted, one or more adjacent rows to a target row corresponding to the sampling address, and selectively refreshing, when the target refresh command is inputted, one or more adjacent rows to a paired row of the target row according to the pairing flag.Type: ApplicationFiled: May 25, 2022Publication date: July 6, 2023Inventors: Chul Moon JUNG, Woongrae KIM
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Publication number: 20230178137Abstract: An integrated circuit includes: first and second pattern generation circuits generating first and second pattern signal for a sampling section; a first section control part generating a coarse section signal for a first section of the sampling section, according to the first pattern signal; a first filter part generating a first section extract signal by filtering the second pattern signal according to the coarse section signal; a second section control part generating a fine section signal for a second section of the sampling section, according to the first section extract signal; a second filter part generating a second section extract signal by filtering the second pattern signal according to the fine section signal; an output control circuit generating a sampling enable signal according to the first and second section extract signals; and a sampling circuit suitable for sampling an input signal according to the sampling enable signal.Type: ApplicationFiled: March 24, 2022Publication date: June 8, 2023Inventors: Woongrae KIM, Byeong Yong GO, Chul Moon JUNG, Yoonna OH
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Publication number: 20230118249Abstract: A memory device may include: a memory bank comprising a plurality of memory blocks, each divided into a normal area and a row hammer area, a command control circuit suitable for performing an access operation on the normal area in response to an active command, an internal command generation circuit suitable for generating an internal command in response to a precharge command, a target address generation circuit suitable for saving a count for each logic level combination of a received address in the row hammer area by performing an access operation on the row hammer area in response to the internal command, and setting an address corresponding to the count as a target address when the count satisfies a preset condition, and a refresh control circuit suitable for controlling a smart refresh operation on the target address.Type: ApplicationFiled: April 28, 2022Publication date: April 20, 2023Inventors: Byeong Yong GO, Woongrae KIM, Hoiju CHUNG, Saeng Hwan KIM, Yoonna OH, Chul Moon JUNG
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Publication number: 20230067759Abstract: A fuse latch of a semiconductor device including PMOS transistors and NMOS transistors includes a data transmission circuit configured to transmit data to a first node and a second node in response to a first control signal, a latch circuit configured to latch the data received from the data transmission circuit through the first node and the second node, and a data output circuit configured to output the data latched by the latch circuit in response to a second control signal. NMOS transistors contained in the data transmission circuit, the latch circuit, and the data output circuit may be formed in first, fourth, and fifth active regions, PMOS transistors are formed in second and third active regions, and the first to fifth active regions are sequentially arranged in a first direction.Type: ApplicationFiled: December 20, 2021Publication date: March 2, 2023Inventors: Jae Hwan SEO, Chul Moon JUNG
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Publication number: 20220230667Abstract: Disclosed is a word line control circuit including a first driving unit configured to apply a first power supply voltage or a second power supply voltage to a word line according to a first word line control signal; a second driving unit configured to drop a voltage level of the word line to a first target level during a first period by using a third power supply voltage according to output of the first driving unit and a second word line control signal; and a third driving unit configured to maintain the voltage level of the word line at substantially the first target level during a second period according to a third word line control signal, and to drop the voltage level of the word line to a second target level during a third period by using a fourth power supply voltage.Type: ApplicationFiled: June 2, 2021Publication date: July 21, 2022Inventors: Chul Moon JUNG, Duck Hwa HONG
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Publication number: 20220199186Abstract: A memory system includes: an address scrambler suitable for scrambling an address based on a scrambling rule to generate a scrambled address; a memory core including a plurality of memory cells and suitable for storing data in memory cells designated by the scrambled address; and a scramble control circuit suitable for changing the scrambling rule in response to satisfaction of an attack condition.Type: ApplicationFiled: December 13, 2021Publication date: June 23, 2022Inventors: Chul Moon JUNG, Uk Song KANG, Woongrae KIM
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Publication number: 20220188015Abstract: A semiconductor memory device comprises: first storage logic configured to store, as first addresses, ‘K’ addresses having different values among input addresses applied during the enable period of a reference signal, second storage logic configured to store, as second addresses, ‘L’ addresses corresponding to a time point at which the enable period of the reference signal is ended among the input addresses, an order controller configured to determine a first output order of each of the first addresses based on a number of times each of the first addresses is repeatedly input, and to determine a second output order for outputting mixed addresses obtained by mixing the first addresses based on the first output order and the second addresses together, and refresh operation logic configured to apply the mixed addresses according to the second output order, to a target refresh operation.Type: ApplicationFiled: December 13, 2021Publication date: June 16, 2022Inventors: Woongrae KIM, Kwi Dong KIM, Chul Moon JUNG, Jeong Tae HWANG
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Patent number: 11107544Abstract: A non-volatile storage device includes a non-volatile storage circuit including a plurality of fuse sets suitable for sequentially outputting fuse data according to a counting address, each fuse set including an enable fuse, a plurality of address fuses, and a duplication fuse; a read control circuit suitable for receiving the fuse data, and outputting latch data by selectively masking data of the enable fuse and the address fuses using data of the duplication fuse within the received fuse data; and a program control circuit suitable for controlling programming the duplication fuse of a duplicated fuse set among the fuse sets when a repair address inputted from outside is identical to data of the address fuses within the duplicated fuse set, or to program the repair address into an available fuse set among the fuse sets, according to a program mode signal.Type: GrantFiled: May 13, 2020Date of Patent: August 31, 2021Assignee: SK hynix Inc.Inventor: Chul-Moon Jung
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Publication number: 20210193241Abstract: A non-volatile storage device includes a non-volatile storage circuit including a plurality of fuse sets suitable for sequentially outputting fuse data according to a counting address, each fuse set including an enable fuse, a plurality of address fuses, and a duplication fuse; a read control circuit suitable for receiving the fuse data, and outputting latch data by selectively masking data of the enable fuse and the address fuses using data of the duplication fuse within the received fuse data; and a program control circuit suitable for controlling programming the duplication fuse of a duplicated fuse set among the fuse sets when a repair address inputted from outside is identical to data of the address fuses within the duplicated fuse set, or to program the repair address into an available fuse set among the fuse sets, according to a program mode signal.Type: ApplicationFiled: May 13, 2020Publication date: June 24, 2021Inventor: Chul-Moon JUNG
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Publication number: 20200327951Abstract: In one embodiment of the present disclosure, an OTP memory circuit may include: a fuse array configured to output fuse data of a fuse set corresponding to a fuse address among a plurality of fuse sets; and a fuse address generation circuit configured to generate the fuse address to search for an available fuse set within a particular region, corresponding to a defective address, among a plurality of regions of the fuse array.Type: ApplicationFiled: December 10, 2019Publication date: October 15, 2020Applicant: SK hynix Inc.Inventor: Chul Moon JUNG
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Patent number: 10496414Abstract: A semiconductor device may include a fuse array configured to output fuse data. The semiconductor device may include a latch circuit configured to store the fuse data during an enabled section of a dummy boot-up signal, output the stored fuse data as a fuse data information signal during a disabled section of the dummy boot-up signal, and fix the fuse data information signal to a specific level during the enabled section of the dummy boot-up signal regardless of the stored fuse data.Type: GrantFiled: April 10, 2018Date of Patent: December 3, 2019Assignee: SK hynix Inc.Inventors: Chul Moon Jung, Joo Hyeon Lee, Sung Nyou Yu
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Patent number: 10249359Abstract: An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.Type: GrantFiled: March 15, 2017Date of Patent: April 2, 2019Assignee: SK hynix Inc.Inventors: Chul-Moon Jung, Saeng-Hwan Kim
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Publication number: 20190056956Abstract: A semiconductor device may include a fuse array configured to output fuse data. The semiconductor device may include a latch circuit configured to store the fuse data during an enabled section of a dummy boot-up signal, output the stored fuse data as a fuse data information signal during a disabled section of the dummy boot-up signal, and fix the fuse data information signal to a specific level during the enabled section of the dummy boot-up signal regardless of the stored fuse data.Type: ApplicationFiled: April 10, 2018Publication date: February 21, 2019Applicant: SK hynix Inc.Inventors: Chul Moon JUNG, Joo Hyeon LEE, Sung Nyou YU