Abstract: A fuse latch of a semiconductor device including PMOS transistors and NMOS transistors includes a data transmission circuit configured to transmit data to a first node and a second node in response to a first control signal, a latch circuit configured to latch the data received from the data transmission circuit through the first node and the second node, and a data output circuit configured to output the data latched by the latch circuit in response to a second control signal. NMOS transistors contained in the data transmission circuit, the latch circuit, and the data output circuit may be formed in first, fourth, and fifth active regions, PMOS transistors are formed in second and third active regions, and the first to fifth active regions are sequentially arranged in a first direction.

Abstract: Disclosed is a word line control circuit including a first driving unit configured to apply a first power supply voltage or a second power supply voltage to a word line according to a first word line control signal; a second driving unit configured to drop a voltage level of the word line to a first target level during a first period by using a third power supply voltage according to output of the first driving unit and a second word line control signal; and a third driving unit configured to maintain the voltage level of the word line at substantially the first target level during a second period according to a third word line control signal, and to drop the voltage level of the word line to a second target level during a third period by using a fourth power supply voltage.

Abstract: A memory system includes: an address scrambler suitable for scrambling an address based on a scrambling rule to generate a scrambled address; a memory core including a plurality of memory cells and suitable for storing data in memory cells designated by the scrambled address; and a scramble control circuit suitable for changing the scrambling rule in response to satisfaction of an attack condition.

Abstract: A semiconductor memory device comprises: first storage logic configured to store, as first addresses, ‘K’ addresses having different values among input addresses applied during the enable period of a reference signal, second storage logic configured to store, as second addresses, ‘L’ addresses corresponding to a time point at which the enable period of the reference signal is ended among the input addresses, an order controller configured to determine a first output order of each of the first addresses based on a number of times each of the first addresses is repeatedly input, and to determine a second output order for outputting mixed addresses obtained by mixing the first addresses based on the first output order and the second addresses together, and refresh operation logic configured to apply the mixed addresses according to the second output order, to a target refresh operation.

Abstract: A non-volatile storage device includes a non-volatile storage circuit including a plurality of fuse sets suitable for sequentially outputting fuse data according to a counting address, each fuse set including an enable fuse, a plurality of address fuses, and a duplication fuse; a read control circuit suitable for receiving the fuse data, and outputting latch data by selectively masking data of the enable fuse and the address fuses using data of the duplication fuse within the received fuse data; and a program control circuit suitable for controlling programming the duplication fuse of a duplicated fuse set among the fuse sets when a repair address inputted from outside is identical to data of the address fuses within the duplicated fuse set, or to program the repair address into an available fuse set among the fuse sets, according to a program mode signal.

Abstract: A non-volatile storage device includes a non-volatile storage circuit including a plurality of fuse sets suitable for sequentially outputting fuse data according to a counting address, each fuse set including an enable fuse, a plurality of address fuses, and a duplication fuse; a read control circuit suitable for receiving the fuse data, and outputting latch data by selectively masking data of the enable fuse and the address fuses using data of the duplication fuse within the received fuse data; and a program control circuit suitable for controlling programming the duplication fuse of a duplicated fuse set among the fuse sets when a repair address inputted from outside is identical to data of the address fuses within the duplicated fuse set, or to program the repair address into an available fuse set among the fuse sets, according to a program mode signal.

Abstract: In one embodiment of the present disclosure, an OTP memory circuit may include: a fuse array configured to output fuse data of a fuse set corresponding to a fuse address among a plurality of fuse sets; and a fuse address generation circuit configured to generate the fuse address to search for an available fuse set within a particular region, corresponding to a defective address, among a plurality of regions of the fuse array.

Abstract: A semiconductor device may include a fuse array configured to output fuse data. The semiconductor device may include a latch circuit configured to store the fuse data during an enabled section of a dummy boot-up signal, output the stored fuse data as a fuse data information signal during a disabled section of the dummy boot-up signal, and fix the fuse data information signal to a specific level during the enabled section of the dummy boot-up signal regardless of the stored fuse data.

Abstract: An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

Abstract: A semiconductor device may include a fuse array configured to output fuse data. The semiconductor device may include a latch circuit configured to store the fuse data during an enabled section of a dummy boot-up signal, output the stored fuse data as a fuse data information signal during a disabled section of the dummy boot-up signal, and fix the fuse data information signal to a specific level during the enabled section of the dummy boot-up signal regardless of the stored fuse data.

Abstract: A refresh control device for reducing power consumption during a target row refresh operation is disclosed. The refresh control device includes a refresh address generator configured to generate a refresh address by selecting any one of a target row refresh address and a normal refresh address according to a target row refresh flag signal, an address control signal generator configured to generate a multiple address control signal in response to the target row refresh flag signal and a multiple refresh signal, and a final refresh address generator configured to generate a plurality of final refresh addresses from the refresh address in response to the multiple address control signal.

Abstract: A refresh control device for reducing power consumption during a target row refresh operation is disclosed. The refresh control device includes a refresh address generator configured to generate a refresh address by selecting any one of a target row refresh address and a normal refresh address according to a target row refresh flag signal, an address control signal generator configured to generate a multiple address control signal in response to the target row refresh flag signal and a multiple refresh signal, and a final refresh address generator configured to generate a plurality of final refresh addresses from the refresh address in response to the multiple address control signal.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output a clock signal, a test mode signal and command address signals. The second semiconductor device may repeatedly write and read out data into and from a plurality of memory cells sequentially selected by addresses that are sequentially counted or may repeatedly write and read out the data into and from specific memory cells selected by a specific address among the addresses, according to the clock signal and the command address signals in response to the test mode signal.

Abstract: An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

Abstract: A semiconductor device includes a decoded signal generation circuit suitable for executing a counting operation to generate a decoded signal in response to an oscillation signal during a refresh section, a refresh pulse generation circuit suitable for generating a refresh pulse for executing a refresh operation in response to the decoded signal and a temperature code, and a reset pulse generation circuit suitable for generating a reset pulse initializing the decoded signal in response to the refresh pulse.

Abstract: A semiconductor system may include a command processor configured to decode a command to generate an active pulse and a delayed active pulse, and a bank active signal generation circuit configured to generate a bank active signal for performing an active operation for a bank accessed by an address. The bank active signal may be disabled in synchronization with the active pulse and is enabled in synchronization with the delayed active pulse.

Abstract: A semiconductor device includes a decoded signal generation circuit suitable for executing a counting operation to generate a decoded signal in response to an oscillation signal during a refresh section, a refresh pulse generation circuit suitable for generating a refresh pulse for executing a refresh operation in response to the decoded signal and a temperature code, and a reset pulse generation circuit suitable for generating a reset pulse initializing the decoded signal in response to the refresh pulse.

Abstract: A memory device includes a plurality of banks suitable for including a plurality of word lines, a plurality of latch units each suitable for generating a first address by inverting a predetermined bit of an address of an activated word line of a corresponding bank and latching the first address as a target address in sections other than a target refresh section, and latching an operation address as the target address once in an all-bank refresh section of the target refresh section, wherein all of the plurality of banks are refreshed in the all-bank refresh section. All the plurality of banks are refreshed in the all-bank refresh section, and an address operation unit suitable for generating the operation address by adding or subtracting an operation value to or from the target address. A word line among the plurality of word lines that is selected using the target address may be refreshed in the target refresh section.

Abstract: An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

Abstract: A semiconductor system may include a command processor configured to decode a command to generate an active pulse and a delayed active pulse, and a bank active signal generation circuit configured to generate a bank active signal for performing an active operation for a bank accessed by an address. The bank active signal may be disabled in synchronization with the active pulse and is enabled in synchronization with the delayed active pulse.