Abstract: A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor structure over a semiconductor substrate. The method also includes implanting carbon into the semiconductor structure. The method further includes implanting gallium into the semiconductor structure. In addition, the method includes heating the semiconductor structure after the implanting of carbon and gallium.

Abstract: FinFET structures and methods of forming the same are disclosed. A device includes a semiconductor fin. A gate stack is on the semiconductor fin. The gate stack includes a gate dielectric on the semiconductor fin and a gate electrode on the gate dielectric. The gate electrode and the gate dielectric have top surfaces level with one another. A first inter-layer dielectric (ILD) is adjacent the gate stack over the semiconductor fin. The first ILD exerts a compressive strain on the gate stack.

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes following operations. A plurality of fin structures and a plurality of trenches are formed over a semiconductor substrate, wherein the fin structures are spaced apart by the trenches, and the fin structures are covered by a mask layer. A dielectric layer is formed over the substrate, wherein the dielectric layer is in the plurality of trenches. The dielectric layer is annealed. A plurality of dopants in the dielectric layer are formed when the fin structures are covered by the mask layer.

Abstract: Embodiments described herein relate generally to methods for forming a mask for patterning a feature in semiconductor processing. In an embodiment, a dielectric layer is formed over a substrate. A mask is formed over the dielectric layer. Forming the mask includes depositing a first layer over the dielectric layer; implanting in a first implant process a dopant species through a patterned material and into the first layer at a first energy; after implanting in the first implant process, implanting in a second implant process the dopant species through the patterned material and into the first layer at a second energy greater than the first energy; and forming mask portions of the mask comprising selectively removing portions of the first layer that are not implanted with the dopant species.

Abstract: An embodiment is a method of manufacturing a semiconductor device. The method includes forming a fin on a substrate. A gate structure is formed over the fin. A recess is formed in the fin proximate the gate structure. A gradient doped region is formed in the fin with a p-type dopant. The gradient doped region extends from a bottom surface of the recess to a vertical depth below the recess in the fin. A source/drain region is formed in the recess and on the gradient doped regions.

Abstract: Embodiments described herein relate generally to methods for forming a mask for patterning a feature in semiconductor processing. In an embodiment, a dielectric layer is formed over a substrate. A mask is formed over the dielectric layer. Forming the mask includes depositing a first layer over the dielectric layer; implanting in a first implant process a dopant species through a patterned material and into the first layer at a first energy; after implanting in the first implant process, implanting in a second implant process the dopant species through the patterned material and into the first layer at a second energy greater than the first energy; and forming mask portions of the mask comprising selectively removing portions of the first layer that are not implanted with the dopant species.

Abstract: A method for forming a semiconductor structure comprises heating a solid material to form a gaseous substance; ionizing the gaseous substance to produce a first type of ions; and implanting the first type of ions into a semiconductor substrate. The method can achieve better abruptness, better shallow junction depth, and better sheet resistance.

Abstract: A finFET device and methods of forming a finFET device are provided. The method includes forming a first gate spacer is formed over a dummy gate of a fin field effect transistor (finFET). The method also includes performing a carbon plasma doping of the first gate spacer. The method also includes forming a plurality of source/drain regions, where a source/drain region is disposed on opposite sides of the dummy gate. The method also includes removing dummy gate.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes following operations. A plurality of fin structures and a plurality of trenches are formed over a semiconductor substrate, wherein the fin structures are spaced apart by the trenches, and the fin structures are covered by a mask layer. A dielectric layer is formed over the substrate, wherein the dielectric layer is in the plurality of trenches. The dielectric layer is annealed. A plurality of dopants in the dielectric layer are formed when the fin structures are covered by the mask layer.

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a divergent ion beam is utilized to implant ions into a capping layer, wherein the capping layer is located over a first metal layer, a dielectric layer, and an interfacial layer over a semiconductor fin. The ions are then driven from the capping layer into one or more of the first metal layer, the dielectric layer, and the interfacial layer.

Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

Abstract: In a method for manufacturing a semiconductor device, fin structures each having an upper portion and a lower portion, are formed. The lower portion is embedded in an isolation insulating layer disposed over a substrate and the upper portion protrudes the isolation insulating layer. A gate dielectric layer is formed over the upper portion of each of the fin structures. A conductive layer is formed over the gate dielectric layer. A cap layer is formed over the conductive layer. An ion implantation operation is performed on the fin structures with the cap layer. The ion implantation operation is performed multiple times using different implantation angles to introduce ions into one side surface of each of the fin structures.

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a divergent ion beam is utilized to implant ions into a capping layer, wherein the capping layer is located over a first metal layer, a dielectric layer, and an interfacial layer over a semiconductor fin. The ions are then driven from the capping layer into one or more of the first metal layer, the dielectric layer, and the interfacial layer.

Abstract: A method of forming MOS transistor includes the steps of performing a pocket implantation process on a substrate having a gate stack, performing a co-implanted ion implantation process on the substrate at a temperature less than room temperature, performing a lightly doped source/drain implantation process on the substrate, and forming source and drain regions in the substrate, adjacent the gate stack.

Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

Abstract: A method includes providing a semiconductor substrate, and performing an ion implantation process to a surface of the substrate. The ion implantation process includes intermittently applying an ion beam to the surface, and while applying the ion beam, applying a heating process with a heating temperature above a threshold level.