Patents by Inventor Chun-Fu Chen

Chun-Fu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9122907
    Abstract: A cell image segmentation method includes receiving a cell image, performing a nuclei initialization step to find an internal marker and an external marker to obtain a potential nuclei and a potential cell boundary, calculating a gradient map of the received cell image, performing a filtering step on the gradient map to generate a filtered gradient map, performing a nuclei detection step to obtain a segmented nuclei, and performing a nuclei validation step to obtain a valid nuclei. The nuclei initialization step includes performing a blob detection step to obtain a nuclei candidate, an outlier removal step to obtain the internal marker, a distance transform step to obtain a distance map, and a cell boundary initialization step to obtain the external marker. In another embodiment, a nuclear-to-cytoplasmic ratio evaluation method using the above cell image segmentation method is proposed.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: September 1, 2015
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Gwo Giun Lee, Huan-Hsiang Lin, Cheng-Shiun Tsai, Chun-Fu Chen
  • Patent number: 9087378
    Abstract: This invention discloses a method for object tracking, including determination of an area scaling ratio of the object in a video image sequence. In one embodiment, a centroid of the object is determined. One or more directed straight lines are selected, each passing through the centroid, extending from an end of the object's boundary to an opposite end thereof, and having a direction that is upward. A length scaling ratio for each directed straight line is determined by: determining a motion vector for each selected pixel on the line; computing a scalar component of the motion vector projected onto the line; estimating a change of the line's length according to the scalar components obtained for all pixels; and determining the length scaling ratio according to the change of the line's length. The area scaling ratio is computed based on the length scaling ratios for all directed straight lines.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: July 21, 2015
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Chunhui Cui, Chun-Fu Chen, Ciao-Siang Siao, Gwo Giun Lee, Yan Huo
  • Patent number: 9030468
    Abstract: A method for depth map generation is disclosed, capable of generating a depth map corresponding an image signal, for the application of a 2D to 3D image transformation system. In the depth map generated by the disclosed method, each of the plural image regions of the image signal is assigned with a depth value. Besides, by means of comparing the depth map with another depth map of the earlier time point, the disclosed method can generate a modulated depth map, for assigning a depth value to each of the plural image regions of the image signal more precisely. Thus, the transformation performance and efficiency of the 2D to 3D image transformation system are hereby improved.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: May 12, 2015
    Assignee: National Cheng Kung University
    Inventors: Gwo Giun (Chris) Lee, He-Yuan Lin, Ming-Jiun Wang, Chun-Fu Chen
  • Publication number: 20150078648
    Abstract: A cell image segmentation method includes receiving a cell image, performing a nuclei initialization step to find an internal marker and an external marker to obtain a potential nuclei and a potential cell boundary, calculating a gradient map of the received cell image, performing a filtering step on the gradient map to generate a filtered gradient map, performing a nuclei detection step to obtain a segmented nuclei, and performing a nuclei validation step to obtain a valid nuclei. The nuclei initialization step includes performing a blob detection step to obtain a nuclei candidate, an outlier removal step to obtain the internal marker, a distance transform step to obtain a distance map, and a cell boundary initialization step to obtain the external marker. In another embodiment, a nuclear-to-cytoplasmic ratio evaluation method using the above cell image segmentation method is proposed.
    Type: Application
    Filed: December 12, 2013
    Publication date: March 19, 2015
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Gwo Giun Lee, Huan-Hsiang Lin, Cheng-Shiun Tsai, Chun-Fu Chen
  • Patent number: 8969202
    Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is provided. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: March 3, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Yen-Hao Shih, Ying-Tso Chen, Shih-Chang Tsai, Chun-Fu Chen
  • Publication number: 20150048424
    Abstract: A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern.
    Type: Application
    Filed: August 13, 2013
    Publication date: February 19, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Chun TIEN, Ya-Chi CHOU, Hui-Zhong ZHUANG, Chun-Fu CHEN, Ting-Wei CHIANG, Hsiang Jen TSENG
  • Publication number: 20150045683
    Abstract: An electrocardiography signal extraction method includes receiving an electrocardiography signal, detecting a peak of a wave of the electrocardiography signal, separating the wave into left and right waves, normalizing the left wave and a plurality of scales of Gaussian, comparing the normalized left wave with a left part of the normalized scales of Gaussian, acquiring a left part error function, indicating a left minimum comparative error, selecting a left scale of Gaussian with the left minimum comparative error, obtaining a left duration of the wave, normalizing the right wave, comparing the normalized right wave with a right part of the normalized scales of Gaussian, acquiring a right part error function, indicating a right minimum comparative error, selecting a right scale of Gaussian with the right minimum comparative error, obtaining a right duration of the wave, and obtaining an extracted wave.
    Type: Application
    Filed: September 10, 2013
    Publication date: February 12, 2015
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Gwo Giun LEE, Jhen-Yue HU, Chun-Fu CHEN, Jhu-Syuan HO
  • Publication number: 20150045681
    Abstract: An electrocardiography signal extraction method includes receiving an electrocardiography signal, performing a time-frequency transformation on the received electrocardiography signal to generate a corresponding scalogram, selecting a pre-defined R-pertinent scale, performing the time-frequency transformation at the selected pre-defined R-pertinent scale to generate a R-pertinent summarized response, obtaining a R peak position, selecting a pre-defined QRS-pertinent scale, performing the time-frequency transformation at the selected pre-defined QRS-pertinent scale, obtaining a Q peak position and a S peak position of the electrocardiography signal by finding relative maximum negative responses before and behind the R peak position respectively, obtaining a QRSon position and a QRSoff position by finding relative minimum second derivatives of the responses before the Q peak position and behind the S peak position, respectively.
    Type: Application
    Filed: September 6, 2013
    Publication date: February 12, 2015
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Gwo Giun Lee, Jhen-Yue Hu, Chun-Fu Chen, Jhu-Syuan Ho
  • Publication number: 20150035070
    Abstract: An integrated circuit layout includes a first active region, a second active region, a first PODE (poly on OD edge), a second PODE, a first transistor and a second transistor. The first transistor, on the first active region, includes a gate electrode, a source region and a drain region. The second transistor, on the second active region, includes a gate electrode, a source region and a drain region. The first active region and the second active region are adjacent and electrically disconnected with each other. The first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region. The source regions of the first and second transistor are adjacent with the first PODE and the second PODE respectively. The first PODE and the second PODE are sandwiched between source regions of the first transistor and the second transistor.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng, Wei-Yu Chen, Hui-Zhong Zhuang, Shang-Chih Hsieh, Li-Chun Tien
  • Patent number: 8948510
    Abstract: The present invention relates to a method for merging regions in the image/video, capable of merging plural of image regions into an image merging region. In the disclosed method, these image regions are first sequenced basing on their compactness value. Then, one of these image regions is designated as a reference image region, and a merging test process is executed by merging the reference image region with one of the nearby image regions thereof in sequence, for forming a temporal image merging region. Later, the compactness value of the temporal image merging region is compared with the compactness value of the two consisting image regions thereof, respectively. When the compactness value of the temporal image merging region is larger than either one of the compactness value of the two consisting image regions thereof, the temporal image merging region is designated as an image merging region.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: February 3, 2015
    Assignee: National Cheng Kung University
    Inventors: Gwo Giun (Chris) Lee, He-Yuan Lin, Chun-Fu Chen, Ping-Keng Jao
  • Publication number: 20150031194
    Abstract: An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.
    Type: Application
    Filed: October 10, 2014
    Publication date: January 29, 2015
    Inventors: Jen-Hang YANG, Chun-Fu CHEN, Pin-Dai SUE, Hui-Zhong ZHUANG
  • Publication number: 20140327050
    Abstract: An integrated circuit, manufactured by a process having a nominal minimum pitch of metal lines, includes a plurality of metal lines and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines extends along a first direction, and the plurality of metal lines are separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. At least one of the plurality of standard cells has a cell height along the second direction, and the cell height is a non-integral multiple of the nominal minimum pitch.
    Type: Application
    Filed: April 15, 2014
    Publication date: November 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih HSIEH, Hui-Zhong ZHUANG, Ting-Wei CHIANG, Chun-Fu CHEN, Hsiang-Jen TSENG
  • Publication number: 20140327081
    Abstract: A semiconductor structure includes a first active area structure, an isolation structure surrounding the first active area structure, a first polysilicon structure, a first metal structure, and a second metal structure. The first polysilicon structure is over the first active area structure. The first metal structure is directly over a first portion of the first active area structure. The second metal structure is directly over and in contact with a portion of the first polysilicon structure and in contact with the first metal structure.
    Type: Application
    Filed: August 30, 2013
    Publication date: November 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih HSIEH, Hui-Zhong ZHUANG, Ting-Wei CHIANG, Chun-Fu CHEN, Hsiang-Jen TSENG
  • Publication number: 20140327471
    Abstract: An integrated circuit is manufactured by a predetermined manufacturing process having a nominal minimum pitch of metal lines. The integrated circuit includes a plurality of metal lines extending along a first direction and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines is separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. The plurality of standard cells includes a first standard cell configured to perform a predetermined function and having a first layout and a second standard cell configured to perform the predetermined function and having a second layout different than the first layout. The first and second standard cells have a cell height (H) along the second direction, and the cell height being a non-integral multiple of the nominal minimum pitch.
    Type: Application
    Filed: October 11, 2013
    Publication date: November 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih HSIEH, Hui-Zhong ZHUANG, Ting-Wei CHIANG, Chun-Fu CHEN, Hsiang-Jen TSENG
  • Patent number: 8872269
    Abstract: An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Hang Yang, Chun-Fu Chen, Pin-Dai Sue, Hui-Zhong Zhuang
  • Patent number: 8774503
    Abstract: A method for color feature extraction extracts a color feature vector representative of the color of each image pixel contained in an image signal. The method comprises: receiving the image signal; mapping the image signal to a color space model, where the color of each of the plural image pixels is represented by a first parameter, a second parameter, and a third parameter; obtaining an adjusted second parameter; clustering the plural image pixels into plural color regions or plural fuzzy regions of a color plane of the color space model; and designating the color feature vector to each of the plural image pixels based on the clustering result.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: July 8, 2014
    Assignee: National Cheng Kung University
    Inventors: Gwo Giun (Chris) Lee, He-Yuan Lin, Ming-Jiun Wang, Chun-Fu Chen
  • Patent number: 8774502
    Abstract: A method for image/video segmentation, capable of segmenting an image signal for obtaining plural texture color feature regions, by utilizing both of the advantages carried by the texture feature and the color feature is disclosed. The method comprises the following steps: (A) receiving an image signal including plural image pixels; (B) executing a Gabor filtering process and a value operation process on each of the plural image pixels; (C) designating each of the plural image pixels a corresponding texture feature vector basing on the result of the value operation process; (D) executing a segmentation process on the image signal basing on the texture feature vector of each of the plural image pixels, for obtaining plural texture feature regions; and (E) executing a re-segmentation process on plural color feature regions basing on the distribution of the plural texture feature regions, for obtaining plural texture color feature regions.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: July 8, 2014
    Assignee: National Cheng Kung University
    Inventors: Gwo Giun (Chris) Lee, Chun-Fu Chen, He-Yuan Lin
  • Publication number: 20140167208
    Abstract: A semiconductor device includes a substrate having a first and second region, a first structure and a second structure. The first structure is formed over the substrate in the first region. The first structure has a first height. The second structure is formed over the substrate in the second region. The second structure has a second height different from the first height.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yi Sheng CHENG, Chun Fu CHEN, Yung Tai HUNG, Chin Ta SU
  • Publication number: 20140154881
    Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is provided. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.
    Type: Application
    Filed: February 7, 2014
    Publication date: June 5, 2014
    Applicant: Macronix International Co., Ltd.
    Inventors: Yen-Hao Shih, Ying-Tso Chen, Shih-Chang Tsai, Chun-Fu Chen
  • Patent number: 8674410
    Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is proviced. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: March 18, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Yen-Hao Shih, Ying-Tso Chen, Shih-Chang Tsai, Chun-Fu Chen