Patents by Inventor Chun-Han Chen

Chun-Han Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210288233
    Abstract: A light emitting diode (LED) package structure includes a circuit board, a reflective cup, a LED chip and a lens structure. The reflective cup is mounted on the circuit board, wherein the reflective cup and the circuit board collectively form a concave cup with an opening. The reflective cup has a first metal ring in the concave cup. The LED chip is mounted on the circuit board and within the concave cup. The lens structure has a second metal ring configured to join the first metal ring to cover the opening.
    Type: Application
    Filed: March 8, 2021
    Publication date: September 16, 2021
    Inventors: Chang-Han CHEN, Chun-Peng LIN, Lung-Kuan LAI
  • Publication number: 20210257483
    Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottommost surface of the gate structure is closer to the substrate than a bottommost surface of the source/drain contact.
    Type: Application
    Filed: October 30, 2020
    Publication date: August 19, 2021
    Inventors: Jia-Heng Wang, Chun-Han Chen, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20210249357
    Abstract: An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer are independently comprises silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 12, 2021
    Inventors: Kun-Ju Li, Jhih-Yuan Chen, Hsin-Jung Liu, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Fu-Chun Hsiao, Ji-Min Lin, Chun-Han Chen
  • Publication number: 20210183696
    Abstract: In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.
    Type: Application
    Filed: February 8, 2021
    Publication date: June 17, 2021
    Inventors: Chun-Han Chen, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chung-Ting Ko, Jr-Hung Li, Chi On Chui
  • Publication number: 20210098594
    Abstract: A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.
    Type: Application
    Filed: September 30, 2019
    Publication date: April 1, 2021
    Inventors: Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 10943818
    Abstract: In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Han Chen, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chung-Ting Ko, Jr-Hung Li, Chi On Chui
  • Publication number: 20210005522
    Abstract: The present disclosure relates to a semiconductor device package, which includes a carrier, a lid, a first adhesive layer and a constraint structure. The carrier includes a surface and a first conductive pad on the surface of the carrier. The lid includes a first portion and a second portion separated from the first portion on the surface of the carrier. The first conductive pad is disposed between the first portion of the lid and the surface of the carrier. The first adhesive layer includes a first portion between the first portion of the lid and the first conductive pad. The constraint structure surrounds the first adhesive layer.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Han CHEN, Hsun-Wei CHAN, Mei-Yi WU
  • Publication number: 20210005602
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a first gate structure formed over a fin structure, and a conductive layer formed over the first gate structure. The FinFET device structure includes a first capping layer formed over the conductive layer, and a top surface of the conductive layer is in direct contact with a bottom surface of the first capping layer.
    Type: Application
    Filed: September 17, 2020
    Publication date: January 7, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Han CHEN, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG, Jr-Hung LI, Bo-Cyuan LU
  • Publication number: 20200405751
    Abstract: An ophthalmic product having a cornea repair function includes an ophthalmic composition. The ophthalmic composition includes gold nanoparticles serving as the main repairing ingredient and at least one auxiliary repairing ingredient. The effective concentration of the gold nanoparticles is from 0.01 ppm to 3000 ppm. The content of the at least one auxiliary repairing ingredient is greater than 0 wt % and less than 20 wt % based on 100 wt % of the ophthalmic composition.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 31, 2020
    Inventors: CHUN-HAN CHEN, WAN-YING GAO
  • Publication number: 20200405636
    Abstract: An ophthalmic product having an antioxidative function includes an ophthalmic composition. The ophthalmic composition includes gold nanoparticles and at least one antioxidative auxiliary ingredient. The effective concentration of the gold nanoparticles is from 0.01 ppm to 3000 ppm. The content of the at least one antioxidative auxiliary ingredient is greater than 0 wt % and less than 20 wt % based on 100 wt % of the ophthalmic composition.
    Type: Application
    Filed: June 9, 2020
    Publication date: December 31, 2020
    Inventors: CHUN-HAN CHEN, WAN-YING GAO
  • Patent number: 10804173
    Abstract: The present disclosure relates to a semiconductor device package, which includes a carrier, a lid, a first adhesive layer and a constraint structure. The carrier includes a surface and a first conductive pad on the surface of the carrier. The lid includes a first portion and a second portion separated from the first portion on the surface of the carrier. The first conductive pad is disposed between the first portion of the lid and the surface of the carrier. The first adhesive layer includes a first portion between the first portion of the lid and the first conductive pad. The constraint structure surrounds the first adhesive layer.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: October 13, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Han Chen, Hsun-Wei Chan, Mei-Yi Wu
  • Patent number: 10797050
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a first gate structure formed over a fin structure, and a first capping layer formed over the first gate structure. The FinFET device structure includes a first etching stop layer formed over the first capping layer and the first gate structure, and a top surface and a sidewall surface of the first capping layer are in direct contact with the first etching stop layer.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
  • Patent number: 10770624
    Abstract: A semiconductor package includes a first substrate having a first surface, a second substrate on the first surface of the first substrate, the second substrate having a first surface and a second surface adjacent to the first surface, and the first surface of the second substrate being disposed on the first surface of the first substrate, and a light source on the second surface of the second substrate. A method for manufacturing the semiconductor device package is also provided.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: September 8, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang Chin Tsai, Chun-Han Chen, Hsin-Ying Ho
  • Publication number: 20200135550
    Abstract: In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.
    Type: Application
    Filed: June 3, 2019
    Publication date: April 30, 2020
    Inventors: Chun-Han Chen, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chung-Ting Ko, Jr-Hung Li, Chi On Chui
  • Patent number: 10624897
    Abstract: The invention provides a series of chlorobenzene substituted azaaryl compounds having activity in inhibiting cancer cell growth and low toxicity to normal cells. Particularly, the compounds of the invention have stronger inhibition effect on bladder cancer and liver cancer.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: April 21, 2020
    Assignee: Taipei Medical University
    Inventors: Yun Yen, Jing-Ping Liou, Chun-Han Chen
  • Publication number: 20200043924
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a first gate structure formed over a fin structure, and a first capping layer formed over the first gate structure. The FinFET device structure includes a first etching stop layer formed over the first capping layer and the first gate structure, and a top surface and a sidewall surface of the first capping layer are in direct contact with the first etching stop layer.
    Type: Application
    Filed: October 8, 2019
    Publication date: February 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Han CHEN, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG, Jr-Hung LI, Bo-Cyuan LU
  • Patent number: 10475788
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a first gate structure formed over the fin structure. The FinFET device structure also includes a first capping layer formed over the first gate structure and a first etching stop layer over the first capping layer and the first gate structure. The FinFET device structure further includes a first source/drain (S/D) contact structure formed over the fin structure and adjacent to the first gate structure. A portion of the first etching stop layer which is directly above the first capping layer is higher than another portion of the first etching stop layer which is directly above the first gate spacer layer.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
  • Publication number: 20190194701
    Abstract: A method for producing butyric acid and/or a butyrate is provided, wherein the method comprises fermenting a saccharide-containing substrate in the presence of a first strain and a second strain, wherein the first strain is a butyric acid bacterium and the second strain is at least one of a homofermentative lactic acid bacterium and a facultative heterofermentative lactic acid bacterium.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 27, 2019
    Inventors: Chiang-Hsiung TONG, Chun-Han CHEN, Wan-Shan CHIEN, Ruey-Fu SHIH, Jheng-Jin LUO
  • Publication number: 20190164960
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a first gate structure formed over the fin structure. The FinFET device structure also includes a first capping layer formed over the first gate structure and a first etching stop layer over the first capping layer and the first gate structure. The FinFET device structure further includes a first source/drain (S/D) contact structure formed over the fin structure and adjacent to the first gate structure. A portion of the first etching stop layer which is directly above the first capping layer is higher than another portion of the first etching stop layer which is directly above the first gate spacer layer.
    Type: Application
    Filed: November 24, 2017
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Han CHEN, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG, Jr-Hung LI, Bo-Cyuan LU
  • Patent number: 10297632
    Abstract: A design method for an image sensor device includes providing an initial design for an image sensor device. The initial design includes a pixel array region and a through-via region disposed proximate the pixel array region. The initial design has a first length between the pixel array region and the through-via region. The initial design has a second length that is a width of the through-via region. The design method includes analyzing a ratio of the second length and the first length, and modifying the initial design to achieve a ratio of the second length and the first length within a particular range.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chun-Han Chen, Szu-Ying Chen, Dun-Nian Yaung