Patents by Inventor Chun-Hsia Chen

Chun-Hsia Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230326843
    Abstract: An electric contact structure includes an intermediate plate, spacer bars and a carrier plate. The spacer bars are sandwiched between the intermediate plate and the carrier plate. Wires are embedded in the intermediate plate, the spacer bars and the carrier plate. The wires in the spacer bars connect the wires in both the intermediate plate and the carrier plate to compose a three-dimensional connecting circuit. At least one end of each of the wires in the spacer bars is formed with a protrusive contact. An end of each of the wires in the intermediate plate or the carrier plate is formed with a cavity. The bottom of each cavity is provided with a disk contact connecting with one of the wires. Each protrusive contact is embedded into one of the cavities to form electric connection with corresponding one of the disk contacts.
    Type: Application
    Filed: April 7, 2022
    Publication date: October 12, 2023
    Inventor: Chun-Hsia Chen
  • Publication number: 20230147337
    Abstract: An LTCC package structure includes an interposer, two separators, a chip and a substrate. Chip I/O contacts and chip signal pathway nodes are disposed on a central portion and a peripheral portion of the interposer, respectively. The chip I/O contacts are electrically connected to the chip signal pathway nodes through transmission wires embedded in the interposer. The separators are provided with multiple signal junction wires therein. The chip is superposed on or under the interposer and electrically connected to the chip I/O contacts. Signal junction nodes are disposed on an upper surface of the substrate. Signal output contacts are disposed on a bottom surface of the substrate. The signal junction nodes are electrically connected to the signal output contacts through transmission wires embedded in the substrate. The substrate is superposed under the separators. The signal junction wires are electrically connected to the signal junction nodes.
    Type: Application
    Filed: November 6, 2021
    Publication date: May 11, 2023
    Applicant: ONANO INDUSTRIAL CORP.
    Inventor: Chun-Hsia Chen
  • Publication number: 20230131658
    Abstract: An LTCC package structure includes an interposer, a semiconductor chip and a substrate. The interposer has a chamber therein. Multiple chip input/output (I/O) contacts are formed in the chamber. The chip I/O contacts are electrically connected to connecting wires disposed at a peripheral area of the interposer through transmission wires embedded in the interposer. The semiconductor chip is disposed in the chamber and electrically connected to the chip I/O contacts. Multiple signal contacts are disposed on a peripheral portion of an upper surface of the substrate. Multiple external contacts are disposed on a bottom surface of the substrate. The signal contacts are electrically connected to the external contacts through transmission wires embedded in the substrate. The signal contacts of the substrate separately electrically connect with the connecting wires of the interposer.
    Type: Application
    Filed: October 27, 2021
    Publication date: April 27, 2023
    Applicant: ONANO INDUSTRIAL CORP.
    Inventor: Chun-Hsia Chen
  • Publication number: 20230126956
    Abstract: A method includes the steps of: a) providing an interposer, wherein the interposer has a chamber therein, multiple chip I/O contacts are formed in the chamber, and the chip I/O contacts are connected to connecting wires disposed in the interposer through transmission wires in the interposer; b) placing a semiconductor chip in the chamber and electrically connecting pins of the semiconductor chip to the chip I/O contacts; c) providing a substrate, wherein signal contacts and external contacts are disposed on two sides of the substrate, respectively, and the signal contacts are electrically connected to the external contacts through transmission wires embedded in the substrate; d) superposing the interposer on the substrate to form a combination, wherein the signal contacts of the substrate separately electrically connect with the connecting wires of the interposer; and e) encapsulating the combination with encapsulation adhesive.
    Type: Application
    Filed: October 27, 2021
    Publication date: April 27, 2023
    Applicant: ONANO INDUSTRIAL CORP.
    Inventor: Chun-Hsia Chen
  • Publication number: 20230070377
    Abstract: An LTCC integrated circuit mold unit includes an integrated mold formed by multiple circuit mold units which are superposed, electrodes sheathed in the integrated mold and conductive wire sections sheathed in the integrated mold. Each circuit mold unit is formed by a ceramic base with an electrode pattern recess and a through hole. A denting depth of the electrode pattern recess is between 0.5 ?m and 5000 ?m. The through hole penetrates through the ceramic base. An inner diameter of the through hole is above 10 ?m. The electrode pattern recess is filled with a conductive material to form one of the electrodes. Each through hole is filled with the conductive material to form one of the conductive wire sections. The conductive wire sections which are vertically adjacent are connected to form a conductive path. The conductive path electrically connects to at least one of the electrodes.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 9, 2023
    Applicant: ONANO INDUSTRIAL CORP.
    Inventor: Chun-Hsia Chen
  • Publication number: 20220367363
    Abstract: A low temperature co-fired ceramic (LTCC) electronic device includes a template layer, a base layer and a conductor. The template layer and the base layer are ceramic layers. The template layer has an electrode pattern formed by a hollow groove. A depth of the hollow groove is between 10 ?m and 120 ?m, and a width of the hollow groove is above 80 ?m. The base layer is closely overlapped with the template layer. An overlapping area range of the base layer and the template layer at least covers the electrode pattern. The conductor is filled in the hollow groove of the electrode pattern. A filling thickness of the conductor is above 10 ?m.
    Type: Application
    Filed: May 17, 2021
    Publication date: November 17, 2022
    Applicant: ONANO INDUSTRIAL CORP.
    Inventor: Chun-Hsia Chen
  • Patent number: 6229135
    Abstract: An optoelectrical integrated circuit (“IC”) is disclosed. The relay comprises an observing opening on the surface for facilitating the determination whether the relay is normally operated by means of observing the internal elements.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: May 8, 2001
    Assignee: Cosmo Electronics Corp.
    Inventor: Chun-Hsia Chen
  • Patent number: 5714247
    Abstract: A non-specular reflecting surface for use in a Liquid Crystal Display is obtained by randomly embedding particles in a layer of a resin solution and then baking to hardness. The particles' sizes are approximately the same as the layer's thickness, so a randomly uneven surface is the result. The particles are most commonly, but not necessarily, commercially available plastic microspheres. If a photosensitive resin is selected, it may be shaped into a desired pattern without the need for a separate photoresist and etch step. When a high reflectance metal is deposited onto the resin surface it becomes an effective non-specular reflector.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: February 3, 1998
    Assignee: Industrial Technology Research Institute
    Inventors: Chen-Lung Kuo, Dong-Yuan Goang, Chun-hsia Chen