Patents by Inventor Chun-Hsien Huang

Chun-Hsien Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230029508
    Abstract: Some implementations described herein provide a gas curtain system. The gas curtain system includes various components to prevent a gas flowing within a chamber of an interface tool from flowing through an opening into a transport carrier adjacent to the interface tool. The gas curtain system may include a gas distribution component along an edge of the opening that generates a flow of another gas across the opening towards an opposite edge of the opening. In this way, the gas from the chamber is prevented from entering the transport carrier. By preventing the gas from the chamber from entering the transport carrier, a relative humidity within an environment of the transport carrier is maintained such that condensation of moisture on one or more semiconductor wafers within the transport carrier is mitigated.
    Type: Application
    Filed: May 5, 2022
    Publication date: February 2, 2023
    Inventors: Yu-Syuan TSAI, Chen-Yuan KAO, Chia-Han LAI, Hong-Ming WU, Yu-Chan TSAI, Chun-Hsien HUANG, Ken-Yu CHANG
  • Publication number: 20230018513
    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 19, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
  • Publication number: 20230020795
    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 19, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
  • Patent number: 11545392
    Abstract: A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness T1 at a first end of the opening, and a thickness T2 at a second end of the opening, and R1 is a ratio of T1 to T2. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness T3 at the first end of the opening, a thickness T4 at the second end of the opening, R2 is a ratio of T3 to T4, and R1 is greater than R2.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang, Li-Hsien Huang, Darryl Kuo, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 11532495
    Abstract: A chip matching system and a corresponding method are provided. The method defines a plurality of first electronic components in a first wafer as various grades of chips and defines a plurality of second electronic components in a second wafer as various grades of chips, and then grades of the first electronic components and the second electronic components are matched to generate target information, and finally the first and second electronic components are integrated in the same position according to the target information. Therefore, the highest-grade chips can be arranged in a multi-chip module to optimize the quality of the multi-chip module.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: December 20, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wu-Hung Yen, Yi-Hsien Huang, Chun-Tang Lin, Shu-Hua Chen, Shou-Qi Chang
  • Publication number: 20220395666
    Abstract: An oscillating positive expiratory pressure device includes a housing, a top cover, and an oscillating unit. The housing includes a bottom wall and a surrounding wall. The bottom wall has an inclined enclosing surface extending downwardly and terminating at an opening. The oscillating unit is swingably connected to and disposed within the housing. The oscillating unit includes a swing member, and first and second weighting pieces. The swing member includes a swing arm, and first and second swing blocks connected to the swing arm. The first weighting piece is carried on the first swing block. The second weighting piece is carried on the second swing block. The swing arm is swingable to move the second swing block to block and unblock the opening.
    Type: Application
    Filed: June 8, 2022
    Publication date: December 15, 2022
    Inventors: Chun-Hung CHEN, Ling-Ling Leonard LIN, Min-Hsien HUANG
  • Patent number: 11527448
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Grant
    Filed: December 27, 2020
    Date of Patent: December 13, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Patent number: 11528832
    Abstract: An electronic device is provided, which is for coupling to another electronic device in a side-by-side manner, and the electronic device includes a substrate, a first thermal dissipation sheet and a thermal dissipation element. The substrate includes a first surface and a second surface. The first thermal dissipation sheet is disposed on the first surface. The thermal dissipation element is disposed on the substrate. The first thermal dissipation sheet is disposed between the thermal dissipation element and the substrate, and the thermal dissipation element at least partially overlaps the first thermal dissipation sheet.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: December 13, 2022
    Assignee: InnoLux Corporation
    Inventors: Wan-Ling Huang, Tzu-Yuan Lin, Geng-Fu Chang, Chun-Hsien Lin, Shu-Ming Kuo, Jui-Feng Ko, Tsau-Hua Hsieh
  • Patent number: 11519674
    Abstract: The present invention provides a gravity high-efficiency heat dissipation apparatus comprising an evaporator and a condenser. The evaporator comprises a housing, an evaporation chamber arranged at the housing, and a skived structure arranged inside the evaporation chamber. The condenser comprises an upper circulating main pipe, a lower circulating main pipe and one or a plurality of condensation pipes having an upper opening and a lower opening fluidly connected to the upper circulating main pipe and the lower circulating main pipe respectively. The upper circulating main pipe is fluidly connected to an upper side of the evaporator via a first connecting pipe and is fluidly connected to an upper side of the evaporation chamber. The lower circulating main pipe is fluidly connected to one side of the evaporator via a second connecting pipe and is fluidly connected to the evaporation chamber. A circumferential side of each of the condensation pipes has one or a plurality of heat dissipation fins formed thereon.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: December 6, 2022
    Assignee: MAN ZAI INDUSTRIAL CO., LTD.
    Inventors: Cheng-Chien Wan, Cheng-Jui Wan, Chun-Hsien Su, Hui-Fen Huang
  • Patent number: 11521929
    Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: December 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin Liang, Chun-I Tsai, Chih-Wei Chang, Chun-Hsien Huang, Hung-Yi Huang, Keng-Chu Lin, Ken-Yu Chang, Sung-Li Wang, Chia-Hung Chu, Hsu-Kai Chang
  • Publication number: 20220367662
    Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.
    Inventors: Shuen-Shin Liang, Chun-I Tsai, Chih-Wei Chang, Chun-Hsien Huang, Hung-Yi Huang, Keng-Chu Lin, Ken-Yu Chang, Sung-Li Wang, Chia-Hung Chu, Hsu-Kai Chang
  • Publication number: 20220359165
    Abstract: Devices and methods for controlling wafer uniformity in plasma-based process is disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a gas distribution plate (GDP) arranged in the process chamber. The housing comprises: a gas inlet configured to receive a process gas, and a gas outlet configured to expel processed gas. The GDP is configured to distribute the process gas within the process chamber. The GDP has a plurality of holes evenly distributed thereon. The GDP comprises a first zone and a second zone. The first zone is closer to the gas outlet than the second zone. At least one hole in the first zone is closed.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Jr-Sheng CHEN, An-Chi LI, Shi-Che HUANG, Chih-Hsien HSU, Zhi-Hao HUANG, Ming Chih WANG, Yu-Pei CHIANG, Chun Yan CHEN
  • Publication number: 20220359168
    Abstract: Devices and methods for controlling wafer uniformity using a gas baffle plate are disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a baffle plate arranged above a wafer in the process chamber. The baffle plate is configured to control plasma distribution on the wafer. The baffle plate has a shape of an annulus that comprises a first annulus sector and a second annulus sector. The first annulus sector has a first inner radius. The second annulus sector has a second inner radius that is different from the first inner radius.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Jr-Sheng CHEN, An-Chi LI, Shih-Che HUANG, Chih-Hsien HSU, Zhi-Hao HUANG, Alex WANG, Yu-Pei CHIANG, Chun Yan Chen
  • Publication number: 20220352020
    Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas.
    Type: Application
    Filed: June 30, 2022
    Publication date: November 3, 2022
    Inventors: Chun-Hsien Huang, I-Li Chen, Pin-Wen Chen, Yuan-Chen Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 11489010
    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 1, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
  • Patent number: 11475952
    Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: October 18, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang, Chun-Yen Tseng, Chun-Chieh Chang
  • Patent number: 11475953
    Abstract: The invention provides a semiconductor layout pattern, the semiconductor layout pattern includes a substrate, a plurality of ternary content addressable memories (TCAM) are arranged on the substrate, the layout of at least two TCAM is mirror symmetric with each other along an axis of symmetry, and the two TCAM are connected to the same search line (SL) together.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: October 18, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Shu-Ru Wang, Chun-Hsien Huang, Hsin-Chih Yu, Meng-Ping Chuang, Li-Ping Huang
  • Patent number: 11455498
    Abstract: A model training method and an electronic device are provided. The method includes the following steps: establishing a brain age prediction model according to a training set; adjusting a parameter in the brain age prediction model according to a validation set; inputting a test set into the brain age prediction model with the adjusted parameter to obtain a plurality of first predicted brain ages; determining whether the first predicted brain ages satisfy a first specific condition; and completing training of the brain age prediction model when the first predicted brain ages satisfy the first specific condition.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: September 27, 2022
    Assignees: Acer Incorporated, National Yang-Ming University
    Inventors: Cheng-Tien Hsieh, Chun-Hsien Yu, Shih-Ho Huang, Meng-Che Cheng, Kun-Hsien Chou, Ching-Po Lin, Liang-Kung Chen
  • Publication number: 20220299418
    Abstract: A gas detection system for gynecological disease detection and a detection method using the same are provided. The gas detection system is configured to detect an analyte from a female vagina and includes: a main body, a sleeve, a detection module, a pump, and a control module. The main body includes a body portion and a head portion having an intake channel. The body portion includes a detection chamber and an exhaust channel. The detection module includes at least one sensor configured to detect at least one target of the analyte and produce at least one detection signal. The pump is communicated with the detection chamber and the exhaust channel. The control module includes a processing unit and a first communication unit. The processing unit receives the at least one detection signal and controls the first communication unit to send the at least one detection signal.
    Type: Application
    Filed: April 20, 2021
    Publication date: September 22, 2022
    Inventors: Chia-Nan Liao, Chia-Pin Huang, Tzu-Ting Weng, Yu-Hsuan Liao, Chun-Hsien Tsai, Ting-Chuan Lee, Chun-Jung Tsai
  • Publication number: 20220293503
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 15, 2022
    Inventors: Chun-Hsien HUANG, Peng-Fu HSU, Yu-Syuan TSAI, Min-Hsiu HUNG, Chen-Yuan KAO, Ken-Yu CHANG, Chun-I TSAI, Chia-Han LAI, Chih-Wei CHANG, Ming-Hsing TSAI