Abstract: An ultrasonic scanning method for an ultrasonic scanning device is provided according to an embodiment of the disclosure. The ultrasonic scanning method includes: performing an ultrasonic scanning operation on a human body by an ultrasonic scanner to obtain an ultrasonic image; analyzing the ultrasonic image by an image recognition module to identify an organ pattern in the ultrasonic image; and generating, automatically, a guiding message according to an identification result of the organ pattern, wherein the guiding message is configured to guide a moving of the ultrasonic scanner to scan a target organ of the human body.

Abstract: An electronic device with a display interface is provided. The electronic device includes a device body and a display module. The device body includes a groove. The display module is disposed on the device body, wherein the display module includes a shaft, the shaft is rotatably connected to the groove and is adapted to be slid in the groove, and the extension direction of the groove differs from the axis of the shaft.

Abstract: The disclosure provides a method for verifying training data, a training system, and a computer program produce. The method includes: receiving a labelled result with a plurality of bounding regions, wherein the labelled result corresponds to an image, the bounding regions are labelled by a plurality of annotators, the annotators comprises a first annotator and a second annotator, and the bounding region comprises a first bounding region labelled by the first annotator and a second bounding region labelled by the second annotator; and determining the first bounding region and the second bounding region respectively corresponds to different two target objects or corresponds to one target object according to a similarity between the first bounding region and the second bounding region.

Abstract: A flip-chip package substrate and a method for fabricating the same are provided. An insulation layer is formed on two opposing sides of a middle layer to form a composite core structure and increase the rigidity of the flip-chip package substrate. Therefore, the core structure can be made thinner. The conductive structures can also have a smaller end size, and more conductive points can be disposed within a unit area. Therefore, a circuit structure can be produced that have a fine line pitch and a high wiring density, satisfy the packaging demands of highly integrated circuit/large size substrate, and avoid an electronic package from being warpage.

Abstract: A flip-chip package substrate and a method for preparing the same in accordance with the present disclosure includes stacking a reinforcement layer on two opposing sides of a middle layer in order to increase the rigidity of the flip-chip package substrate, and promoting a thin middle layer, wherein the sizes of the end faces of conductive portions can be minimized according to needs. This increases the number of electrical contacts possible in a unit area and enables the creation of finer line pitch and higher layout density of the circuit portions, thereby satisfying the need for packaging of high integration/large scale chips while preventing warpage from occurring in the electronic packages.

Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.

Abstract: A semiconductor packaging substrate is provided and includes: an insulating layer, a thinned circuit structure formed of circuit layers and conductive posts stacked on one another embedding in the insulating layer, and a supporting structure formed on the insulating layer and having at least one through hole exposing the conductive posts. As such, before a subsequent packaging operation, the packaging substrate can be electrically tested and screened so as to prevent a defective packaging substrate from being misused in the subsequent packaging operation and hence avoid the loss of normal electronic elements. A method for fabricating a semiconductor packaging substrate and a packaging process using the semiconductor packaging substrate are also provided.

Abstract: A model training method and an electronic device are provided. The method includes the following steps: establishing a brain age prediction model according to a training set; adjusting a parameter in the brain age prediction model according to a validation set; inputting a test set into the brain age prediction model with the adjusted parameter to obtain a plurality of first predicted brain ages; determining whether the first predicted brain ages satisfy a first specific condition; and completing training of the brain age prediction model when the first predicted brain ages satisfy the first specific condition.

Abstract: A flip-chip package substrate and a method for fabricating the same are provided. An insulation layer is formed on two opposing sides of a middle layer to form a composite core structure and increase the rigidity of the flip-chip package substrate. Therefore, the core structure can be made thinner. The conductive structures can also have a smaller end size, and more conductive points can be disposed within a unit area. Therefore, a circuit structure can be produced that have a fine line pitch and a high wiring density, satisfy the packaging demands of highly integrated circuit/large size substrate, and avoid an electronic package from being warpage.

Abstract: This disclosure provides a package substrate including: a first dielectric layer formed of a first molding compound; a first conductive wire and a first conductive channel disposed in the first dielectric layer; a second dielectric layer formed of a second molding compound; a second conductive wire and a second conductive channel disposed in the second dielectric layer; a third dielectric layer formed of a third molding compound; a third conductive wire and a third conductive channel disposed in the third dielectric layer; a fourth dielectric layer formed of a fourth molding compound; a fourth conductive wire, a fourth conductive channel and a circuit device disposed in the fourth dielectric layer; wherein, a first empty region, a second empty region, a third empty region and a fourth empty region are formed in the first, second, third and fourth dielectric layers, respectively, and the empty regions are vertically overlapped.

Abstract: A semiconductor package carrier board, a method for fabricating the same, and an electronic package having the same are provided. The method includes forming on a circuit structure a graphene layer that acts as an insulation heat dissipating layer. Since the heat conductivity of the graphene layer is far greater than the heat conductivity of ink (about 0.4 W/m·k), which is used as solder resist, the heat of the semiconductor package carrier board can be conducted quickly, and thus can avoid the problem that the heat will be accumulated on the semiconductor package carrier board.

Abstract: A semiconductor package substrate, a method for fabricating the same, and an electronic package having the same are provided. The method includes: providing a circuit structure having a first solder pad and a second solder pad; forming on the circuit structure a metal sheet having a first hole, from which the first solder pad is exposed, and a second hole, from which the second solder pad is exposed; and forming an insulation layer on the metal sheet and a hole wall of the second hole. A first conductive element that is to be grounded is disposed in the first hole and is in contact with the metal sheet and the first solder pad. Therefore, heat generated in a signal transmission process is dissipated by the metal sheet and the first conductive element.

Abstract: The disclosure provides a method for training generative adversarial network (GAN), a method for generating images by using GAN, and a computer readable storage medium. The method may train the first generator of the GAN with available training samples belonging to the first type category and share the knowledge learnt by the first generator to the second generator. Accordingly, the second generator may learn to generate (fake) images belonging to the second type category even if there are no available training data during training the second generator.

Abstract: This disclosure provides a package substrate fabrication method including: providing a carrier; forming a first dielectric layer on the carrier while enabling the first dielectric layer to be patterned including an opening; forming a first conducting unit on the carrier while enabling the first conducting unit to fill up the opening, a height of the first conducting unit at the opening larger than a thickness of the first dielectric layer, and a width of the first conducting unit larger than a width of the opening; forming a second dielectric layer on the first conducting unit; forming a second conducting unit on the second dielectric layer; forming a third dielectric layer on the second conducting unit; removing the carrier and the first dielectric layer while enabling the part of the first conducting unit in the opening to be removed; and forming a fourth dielectric layer to cover the first conducting unit.

Abstract: A semiconductor packaging substrate and a method for fabricating the same are provided. The method includes forming a solder resist structure having a hole on a circuit structure, with a portion of the circuit structure exposed from the hole, and forming a cup-shaped solder stand on the exposed circuit layer and a hole wall of the hole. During a packaging process, the design of the solder stand increases a contact area of a solder tin ball with a metal material. Therefore, a bonding force between the solder tin ball and the solder stand is increased, and the solder tin ball can be protected from being broken or fell off. An electronic package having the semiconductor packaging substrate and a method for fabricating the electronic package are also provided.

Abstract: A flexible substrate is provided, including a coreless substrate body having a flexible section, and an additional element formed on the substrate body and having a through hole exposing the flexible section, thereby reducing the overall thickness of the flexible substrate and meeting the thinning requirement

Abstract: This disclosure provides a package substrate fabrication method including: providing a carrier; forming a first dielectric layer on the carrier while enabling the first dielectric layer to be patterned including an opening; forming a first conducting unit on the carrier while enabling the first conducting unit to fill up the opening, a height of the first conducting unit at the opening larger than a thickness of the first dielectric layer, and a width of the first conducting unit larger than a width of the opening; forming a second dielectric layer on the first conducting unit; forming a second conducting unit on the second dielectric layer; forming a third dielectric layer on the second conducting unit; removing the carrier and the first dielectric layer while enabling the part of the first conducting unit in the opening to be removed; and forming a fourth dielectric layer to cover the first conducting unit.

Abstract: An ultrasonic scanning method for an ultrasonic scanning device is provided according to an embodiment of the disclosure. The ultrasonic scanning method includes: performing an ultrasonic scanning operation on a human body by an ultrasonic scanner to obtain an ultrasonic image; analyzing the ultrasonic image by an image recognition module to identify an organ pattern in the ultrasonic image; and generating, automatically, a guiding message according to an identification result of the organ pattern, wherein the guiding message is configured to guide a moving of the ultrasonic scanner to scan a target organ of the human body.

Abstract: The disclosure provides a method for verifying training data, a training system, and a computer program produce. The method includes: providing a plurality of raw data to a plurality of annotators; retrieving a plurality of labelled results, wherein the labelled results includes a plurality of labelled data, and the labelled data are generated by the annotators via labelling the raw data; determining a plurality of consistencies by comparing the labelled results, and accordingly determining whether the labelled results are valid for training an artificial intelligence machine; in response to determining that the labelled results are valid, determining at least a specific part of the labelled results are valid for training the artificial intelligence machine.

Abstract: A flip-chip package substrate and a method for preparing the same in accordance with the present disclosure includes stacking a reinforcement layer on two opposing sides of a core layer in order to increase the rigidity of the flip-chip package substrate, and promoting a thin core layer, wherein the sizes of the end faces of conductive portions can be minimized according to needs. This increases the number of electrical contacts possible in a unit area and enables the creation of finer line pitch and higher layout density of the circuit portions, thereby satisfying the need for packaging of high integration/large scale chips while preventing warpage from occurring in the electronic packages.