Patents by Inventor Chun-Hsiung Lin
Chun-Hsiung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230260793Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. The semiconductor device structure includes a silicide layer between the dielectric fin and the epitaxial structure. A void is between the silicide layer and the dielectric fin.Type: ApplicationFiled: April 21, 2023Publication date: August 17, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsiung LIN, Jung-Hung CHANG, Shih-Cheng CHEN, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20230261114Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Inventors: Pei-Hsun Wang, Chih-Hao Wang, Chun-Hsiung Lin
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Patent number: 11728221Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.Type: GrantFiled: March 15, 2021Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Lun Chen, Chao-Hsien Huang, Li-Te Lin, Chun-Hsiung Lin
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Patent number: 11721594Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.Type: GrantFiled: June 8, 2022Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Wei-Sheng Yun, Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Chao Chou, Chun-Hsiung Lin, Pei-Hsun Wang
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Patent number: 11695076Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.Type: GrantFiled: March 5, 2021Date of Patent: July 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
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Patent number: 11664230Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. The semiconductor device structure includes a silicide layer between the dielectric fin and the epitaxial structure. A distance between the silicide layer and the dielectric fin increases toward the base portion.Type: GrantFiled: August 9, 2021Date of Patent: May 30, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsiung Lin, Jung-Hung Chang, Shih-Cheng Chen, Kuo-Cheng Chiang, Chih-Hao Wang
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Publication number: 20230145872Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.Type: ApplicationFiled: December 14, 2022Publication date: May 11, 2023Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
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Patent number: 11637207Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.Type: GrantFiled: February 15, 2021Date of Patent: April 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Hsun Wang, Chun-Hsiung Lin, Chih-Hao Wang
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Publication number: 20230103862Abstract: A semiconductor device includes a semiconductor substrate, a first epitaxial feature having a first semiconductor material over the semiconductor substrate, and a second epitaxial feature having a second semiconductor material over the semiconductor substrate. The second semiconductor material being different from the first semiconductor material. The semiconductor device further includes a first silicide layer on the first epitaxial feature, a second silicide layer on the second epitaxial feature, a metal layer on the first silicide layer, a first contact feature over the metal layer, and a second contact feature over the second silicide layer. A first number of layers between the first contact feature and the first epitaxial feature is greater than a second number of layers between the second contact feature and the second epitaxial feature.Type: ApplicationFiled: November 28, 2022Publication date: April 6, 2023Inventors: Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
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Publication number: 20230043999Abstract: A method for estimating at least one electrical property of a semiconductor device is provided. The method includes forming the semiconductor device and at least one testing unit on a substrate, irradiating the testing unit with at least one electron beam, estimating electrons from the testing unit induced by the electron beam, and estimating the electrical property of the semiconductor device according to intensity of the estimated electrons from the testing unit.Type: ApplicationFiled: October 24, 2022Publication date: February 9, 2023Inventors: Chen-Han Wang, Chun-Hsiung Lin
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Patent number: 11563104Abstract: A semiconductor device is provided. The semiconductor device includes a fin protruding from a semiconductor substrate and a gate structure over the fin. The semiconductor device also includes a source region and a drain region in the fin and at opposite sides of the gate structure. The semiconductor device further includes a gate spacer on a sidewall of the gate structure. The gate spacer includes an air-gap spacer and a sealing spacer above the air-gap spacer, an upper portion of the gate structure is laterally overlapping with the sealing spacer, and the bottom portion of the gate structure is laterally overlapping with the air gap spacer.Type: GrantFiled: October 19, 2020Date of Patent: January 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hsiung Lin, Pei-Hsun Wang, Chih-Chao Chou, Chia-Hao Chang, Chih-Hao Wang
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Patent number: 11532521Abstract: A semiconductor structure includes a first fin, which includes a first plurality of suspended nanostructures vertically stacked over one another, each of the first plurality of suspended nanostructure having a center portion that has a first cross section, and a second fin, which includes a second plurality of suspended nanostructures vertically stacked over one another, the first plurality of suspended nanostructures and the second plurality of suspended nanostructures having different material compositions, each of the second plurality of suspended nanostructure having a center portion that has a second cross section, wherein a shape or an area of the first cross section is different from that of the second cross section.Type: GrantFiled: December 7, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Sheng Yun, Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Chao Chou, Chun-Hsiung Lin, Pei-Hsun Wang
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Patent number: 11515216Abstract: A semiconductor structure is received that has a first and second fins. A first epitaxial feature is formed on the first fin and has a first type dopant. A first capping layer is formed over the first epitaxial feature. A second epitaxial feature is formed on the second fin and has a second type dopant different from the first type dopant. A first metal is deposited on the second epitaxial feature and on the first capping layer. A first silicide layer is formed from the first metal and the second epitaxial feature, and a second capping layer is formed from the first metal and the first capping layer. The second capping layer is selectively removed. A second metal is deposited on the first epitaxial feature and over the second epitaxial feature. A second silicide layer is formed from the second metal and the first epitaxial feature.Type: GrantFiled: February 3, 2021Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
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Publication number: 20220367701Abstract: Methods for manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate a substrate and channel layers vertically stacked over the substrate. The semiconductor structure also includes a dielectric fin structure formed adjacent to the channel layers and a gate structure abutting the channel layers and the dielectric fin structure. The semiconductor structure also includes a source/drain structure attached to the channel layers and a contact formed over the source/drain structure. The semiconductor structure also includes a Si layer covering a portion of a top surface of the source/drain structure. In addition, the Si layer is sandwiched between the dielectric fin structure and the contact.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Inventors: Chen-Han WANG, Pei-Hsun WANG, Chun-Hsiung LIN, Chih-Hao WANG
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Publication number: 20220367668Abstract: A semiconductor device is provided. The semiconductor device includes a fin protruding from a semiconductor substrate and a gate structure formed across the fin. The semiconductor device also includes a gate spacer formed over a sidewall of the gate structure. The gate spacer includes a sidewall spacer and a sealing spacer formed above the sidewall spacer. In addition, an air gap is vertically sandwiched between the sidewall spacer and the sealing spacer. The semiconductor device further includes a hard mask formed over the gate structure and covering a sidewall of the sealing spacer.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hsiung LIN, Pei-Hsun WANG, Chih-Chao CHOU, Chia-Hao CHANG, Chih-Hao WANG
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Publication number: 20220352345Abstract: A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin; forming a helmet layer lining the gate structure and the semiconductor fin; etching the helmet layer to remove portions of the helmet layer from opposite sidewalls of the gate structure, wherein the remaining helmet layer comprises a first remaining portion on a top surface of the gate structure and a second remaining portion on a top surface of the semiconductor fin; forming a spacer layer covering the gate structure, wherein the spacer layer is in contact with the first remaining portion and the second remaining portion of the remaining helmet layer; etching the spacer layer and the remaining helmet layer to form gate spacers, wherein each of the gate spacers has a stepped sidewall; and forming source/drain epitaxy structures on opposite sides of the gate structure.Type: ApplicationFiled: June 27, 2022Publication date: November 3, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Lun CHEN, Bau-Ming WANG, Chun-Hsiung LIN
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Patent number: 11480606Abstract: A method for estimating at least one electrical property of a semiconductor device is provided. The method includes forming the semiconductor device and at least one testing unit on a substrate, irradiating the testing unit with at least one electron beam, estimating electrons from the testing unit induced by the electron beam, and estimating the electrical property of the semiconductor device according to intensity of the estimated electrons from the testing unit.Type: GrantFiled: June 14, 2016Date of Patent: October 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Han Wang, Chun-Hsiung Lin
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Publication number: 20220336601Abstract: A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.Type: ApplicationFiled: June 29, 2022Publication date: October 20, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Cheng CHEN, Chun-Hsiung LIN, Chih-Hao WANG
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Publication number: 20220328644Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: ApplicationFiled: June 30, 2022Publication date: October 13, 2022Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Publication number: 20220301943Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.Type: ApplicationFiled: June 8, 2022Publication date: September 22, 2022Inventors: Wei-Sheng Yun, Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Chao Chou, Chun-Hsiung Lin, Pei-Hsun Wang