Patents by Inventor Chun-Hsiung Lin

Chun-Hsiung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200105535
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a first dielectric layer over the base portion and a first sidewall of the fin portion. The method includes forming a first spacer layer over the first dielectric layer. The method includes forming a first dielectric fin over the first spacer layer. The method includes forming an epitaxial structure over the fin portion, wherein a void is surrounded by the epitaxial structure, the first dielectric layer, and the first spacer layer. The method includes removing the first spacer layer between the epitaxial structure and the first dielectric fin. The method includes forming a silicide layer over the epitaxial structure, wherein a first lower portion of the silicide layer covers a lower surface of the epitaxial structure and is in the void.
    Type: Application
    Filed: August 13, 2019
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung LIN, Jung-Hung CHANG, Shih-Cheng CHEN, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20200091309
    Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate structure over a substrate, forming a disposable spacer on a sidewall of the gate structure, and forming a source region and a drain region at opposite sides of the gate structure. The method also includes depositing an interlayer dielectric layer around the disposable spacer, and forming a first hard mask on the interlayer dielectric layer. The method further includes removing an upper portion of the gate structure, and removing the disposable spacer to form a trench between the gate structure and the interlayer dielectric layer. In addition, the method includes sealing the trench to form an air-gap spacer, and forming a second hard mask on the gate structure.
    Type: Application
    Filed: November 2, 2018
    Publication date: March 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung LIN, Pei-Hsun WANG, Chih-Chao CHOU, Chia-Hao CHANG, Chih-Hao WANG
  • Publication number: 20200083341
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Publication number: 20200044045
    Abstract: The present disclosure provides a method of semiconductor fabrication that includes forming a semiconductor fin protruding from a substrate, the semiconductor fin including a plurality of first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked, the second semiconductor material being different from the first semiconductor material in composition; forming a first gate stack on the semiconductor fin; forming a recess in the semiconductor fin within a source/drain (S/D) region adjacent to the first gate stack, a sidewall of the first and second semiconductor material layers being exposed within the recess; performing an etching process to the semiconductor fin, resulting in an undercut below the first gate stack; epitaxially growing on the sidewall of the semiconductor fin to fill in the undercut with a semiconductor extended feature of the first semiconductor material; and growing an epitaxial S/D feature from the rece
    Type: Application
    Filed: July 11, 2019
    Publication date: February 6, 2020
    Inventors: Pei-Hsun Wang, Chih-Chao Chou, Chun-Hsiung Lin, Ching-Wei Tsai, Chih-Hao Wang
  • Publication number: 20200043923
    Abstract: A semiconductor device having a first region and a second region is provided. The first region has a first protruding structure and a second protruding structure. The second region has a third protruding structure and a fourth protruding structure. First, second, third, and fourth epi-layers are formed on the first, second, third, and fourth protruding structures, respectively. The first and second epi-layers are covered with a first photoresist layer while leaving the third and fourth epi-layers exposed. A dielectric layer is formed over the first photoresist layer and over the third and fourth epi-layers. A portion of the dielectric layer is covered with a second photoresist layer. The portion of the dielectric layer is formed over the third and fourth epi-layers. Portions of the dielectric layer not protected by the first and second photoresist layers are etched. The first and second photoresist layers are removed.
    Type: Application
    Filed: October 7, 2019
    Publication date: February 6, 2020
    Inventors: Chen-Han Wang, Chun-Hsiung Lin
  • Patent number: 10553718
    Abstract: A device structure includes: a core structure formed on a support, and a shell material formed on the core structure and surrounding at least part of the core structure. The shell material is associated with a first bandgap; the core structure is associated with a second bandgap; and the first bandgap is smaller than the second bandgap. The shell material and the core structure are configured to form a quantum-well channel in the shell material.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Carlos H. Diaz, Chun-Hsiung Lin, Huicheng Chang, Syun-Ming Jang, Chien-Hsun Wang, Mao-Lin Huang
  • Publication number: 20200035805
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung LIN, Chia-Hao CHANG, Chih-Hao WANG, Wai-Yi LIEN, Chih-Chao CHOU, Pei-Yu WANG
  • Publication number: 20200027960
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Inventors: Chun-Hsiung LIN, Chia-Hao CHANG, Chih-Hao WANG, Wai-Yi LIEN, Chih-Chao CHOU, Pei-Yu WANG
  • Patent number: 10535525
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate, a gate structure, a first doped structure, a second doped structure, and a dielectric layer. The method includes forming a through hole in the dielectric layer. The method includes performing a physical vapor deposition process to deposit a first metal layer over the first doped structure exposed by the through hole. The method includes reacting the first metal layer with the first doped structure to form a metal semiconductor compound layer between the first metal layer and the first doped structure. The method includes removing the first metal layer. The method includes performing a chemical vapor deposition process to deposit a second metal layer in the through hole. The method includes forming a conductive structure in the through hole and over the second metal layer.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-An Lin, Chun-Hsiung Lin, Kai-Hsuan Lee, Sai-Hooi Yeong, Cheng-Yu Yang, Yen-Ting Chen
  • Publication number: 20200006515
    Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.
    Type: Application
    Filed: September 10, 2019
    Publication date: January 2, 2020
    Inventors: Yi-Lun Chen, Chao-Hsien Huang, Li-Te Lin, Chun-Hsiung Lin
  • Patent number: 10510860
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Lin, Chia-Hao Chang, Chih-Hao Wang, Wai-Yi Lien, Chih-Chao Chou, Pei-Yu Wang
  • Patent number: 10497792
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Publication number: 20190334008
    Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Inventors: Yi-Lun Chen, Chao-Hsien Huang, Li-Te Lin, Chun-Hsiung Lin
  • Patent number: 10461079
    Abstract: A semiconductor device having a first region and a second region is provided. The first region has a first protruding structure and a second protruding structure. The second region has a third protruding structure and a fourth protruding structure. First, second, third, and fourth epi-layers are formed on the first, second, third, and fourth protruding structures, respectively. The first and second epi-layers are covered with a first photoresist layer while leaving the third and fourth epi-layers exposed. A dielectric layer is formed over the first photoresist layer and over the third and fourth epi-layers. A portion of the dielectric layer is covered with a second photoresist layer. The portion of the dielectric layer is formed over the third and fourth epi-layers. Portions of the dielectric layer not protected by the first and second photoresist layers are etched. The first and second photoresist layers are removed.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Han Wang, Chun-Hsiung Lin
  • Patent number: 10438948
    Abstract: A semiconductor device having a first region and a second region is provided. The first region has a first protruding structure and a second protruding structure. The second region has a third protruding structure and a fourth protruding structure. First, second, third, and fourth epi-layers are formed on the first, second, third, and fourth protruding structures, respectively. The first and second epi-layers are covered with a first photoresist layer while leaving the third and fourth epi-layers exposed. A dielectric layer is formed over the first photoresist layer and over the third and fourth epi-layers. A portion of the dielectric layer is covered with a second photoresist layer. The portion of the dielectric layer is formed over the third and fourth epi-layers. Portions of the dielectric layer not protected by the first and second photoresist layers are etched. The first and second photoresist layers are removed.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: October 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Han Wang, Chun-Hsiung Lin
  • Publication number: 20190267465
    Abstract: A method includes forming a semiconductor fin over a substrate; forming a helmet stack on a top surface of the semiconductor fin; forming a spacer layer over the helmet stack and on opposite sidewalls of the semiconductor fin; and etching the helmet layer and the spacer layer to expose the top surface and the sidewalls of the semiconductor fin.
    Type: Application
    Filed: February 27, 2018
    Publication date: August 29, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Lun CHEN, Bau-Ming WANG, Chun-Hsiung LIN
  • Publication number: 20190131423
    Abstract: A semiconductor device includes a substrate, a bottom semiconductor fin, at least one sidewall structure, a top semiconductor fin, and a gate structure. The bottom semiconductor fin is disposed on the substrate. The sidewall structure protrudes from the semiconductor fin. The top semiconductor fin is disposed on the bottom semiconductor fin. The top semiconductor fin includes a channel portion and at least one source/drain portion. The source/drain portion is disposed between the channel portion and the sidewall structure. The gate structure covers the channel portion of the top semiconductor fin.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 2, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-An LIN, Chun-Hsiung LIN, Chia-Ta YU, Sai-Hooi YEONG, Ching-Fang HUANG, Wen-Hsing HSIEH
  • Patent number: 10276693
    Abstract: A semiconductor device includes a substrate, a bottom semiconductor fin, at least one sidewall structure, a top semiconductor fin, and a gate structure. The bottom semiconductor fin is disposed on the substrate. The sidewall structure protrudes from the semiconductor fin. The top semiconductor fin is disposed on the bottom semiconductor fin. The top semiconductor fin includes a channel portion and at least one source/drain portion. The source/drain portion is disposed between the channel portion and the sidewall structure. The gate structure covers the channel portion of the top semiconductor fin.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-An Lin, Chun-Hsiung Lin, Chia-Ta Yu, Sai-Hooi Yeong, Ching-Fang Huang, Wen-Hsing Hsieh
  • Publication number: 20190067012
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate, a gate structure, a first doped structure, a second doped structure, and a dielectric layer. The method includes forming a through hole in the dielectric layer. The method includes performing a physical vapor deposition process to deposit a first metal layer over the first doped structure exposed by the through hole. The method includes reacting the first metal layer with the first doped structure to form a metal semiconductor compound layer between the first metal layer and the first doped structure. The method includes removing the first metal layer. The method includes performing a chemical vapor deposition process to deposit a second metal layer in the through hole. The method includes forming a conductive structure in the through hole and over the second metal layer.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Chun-An LIN, Chun-Hsiung LIN, Kai-Hsuan LEE, Sai-Hooi YEONG, Cheng-Yu YANG, Yen-Ting CHEN
  • Publication number: 20190067442
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Application
    Filed: November 1, 2017
    Publication date: February 28, 2019
    Inventors: Chun-Hsiung LIN, Chia-Hao CHANG, Chih-Hao WANG, Wai-Yi LIEN, Chih-Chao CHOU, Pei-Yu WANG