Abstract: An electrical impedance tomography system with frequency division multiplexing based data compression comprising electrodes, a connecting line, an electrical impedance tomography chip, a universal serial bus and a computer. The present invention realizes the proposed electrical impedance tomography system by innovative application of frequency division multiplexing technology, and has the advantages of low power consumption and improved hardware overheads. The architecture of the 13-channel electrical impedance tomography chip introduced in the embodiment of the present invention, which applies the frequency division multiplexing based data compression technology, has taped out using CMOS 0.13 micrometer process; the power consumption per channel turns out to be 118 microwatts and the area is 0.87 square millimeters, verifying the effectiveness of the present invention. The present invention can also be migrated to other applications of electrical impedance tomography.

Abstract: An electrical impedance tomography system with frequency division multiplexing based data compression comprising electrodes, a connecting line, an electrical impedance tomography chip, a universal serial bus and a computer. The present invention realizes the proposed electrical impedance tomography system by innovative application of frequency division multiplexing technology, and has the advantages of low power consumption and improved hardware overheads. The architecture of the 13-channel electrical impedance tomography chip introduced in the embodiment of the present invention, which applies the frequency division multiplexing based data compression technology, has taped out using CMOS 0.13 micrometer process; the power consumption per channel turns out to be 118 microwatts and the area is 0.87 square millimeters, verifying the effectiveness of the present invention. The present invention can also be migrated to other applications of electrical impedance tomography.

Abstract: In various embodiments of the present disclosure, there is provided an energy harvesting apparatus, including: an energy harvester for generating electric power from an ambient source; a power conditioning circuit coupled to the output of the energy harvester; including: a boost converter module; a buck-boost converter module; and a power modification control module; wherein the power modification control module is configured to initialize the energy harvesting apparatus from inactivity to a normal energy harvesting state by operating the boost converter module, and operating the buck-boost converter when an output voltage of the power conditioning circuit rises to a predetermined value. A corresponding method of operating an energy harvesting apparatus is provided.

Abstract: Redundant inverters with multiple inverter stages enable lower operating voltages to be used. For example, the use of multiple inverter stages produces a strong “0” or a strong “1” output signal. The strong output signal facilitates self-oscillation of a ring oscillator at lower voltages.

Abstract: Redundant inverters with multiple inverter stages enable lower operating voltages to be used. For example, the use of multiple inverter stages produces a strong “0” or a strong “1” output signal. The strong output signal facilitates self-oscillation of a ring oscillator at lower voltages.

Abstract: According to embodiments of the present invention, a frequency shift keying transmitter is provided.

Abstract: According to embodiments of the present invention, a transmitter is provided. The transmitter includes a frequency shift keying (FSK) circuit, and a phase shift keying (PSK) circuit coupled in series to the FSK circuit, wherein the FSK circuit is configured, in a first mode of operation, to provide a FSK modulated signal to the PSK circuit, and, in a second mode of operation, to provide a fixed frequency signal to the PSK circuit, and wherein the PSK circuit is configured, in the first mode of operation, to transmit the FSK modulated signal, and, in the second mode of operation, to provide a PSK modulated signal based on the fixed frequency signal received from the FSK circuit.

Abstract: According to embodiments of the present invention, a frequency shift keying transmitter is provided.

Abstract: According to embodiments of the present invention, a transmitter is provided. The transmitter includes a frequency shift keying (FSK) circuit, and a phase shift keying (PSK) circuit coupled in series to the FSK circuit, wherein the FSK circuit is configured, in a first mode of operation, to provide a FSK modulated signal to the PSK circuit, and, in a second mode of operation, to provide a fixed frequency signal to the PSK circuit, and wherein the PSK circuit is configured, in the first mode of operation, to transmit the FSK modulated signal, and, in the second mode of operation, to provide a PSK modulated signal based on the fixed frequency signal received from the FSK circuit.

Abstract: In various embodiments of the present disclosure, there is provided an energy harvesting apparatus, including: an energy harvester for generating electric power from an ambient source; a power conditioning circuit coupled to the output of the energy harvester; including: a boost converter module; a buck-boost converter module; and a power modification control module; wherein the power modification control module is configured to initialize the energy harvesting apparatus from inactivity to a normal energy harvesting state by operating the boost converter module, and operating the buck-boost converter when an output voltage of the power conditioning circuit rises to a predetermined value. A corresponding method of operating an energy harvesting apparatus is provided.

Abstract: A fully-integrated tuner for performing signal channel selection and image rejection in an analog cable television system is provided. Various embodiments disclose a tuner including an analog RF section to process an analog RF input signal and generate complex low intermediate frequency digital signals, and a signal processing section configured to reduce image and signal leakage in the complex low intermediate frequency signals. The signal processing section selects a signal channel of the complex low intermediate frequency signals and suppresses channel components adjacent to the signal channel. In one embodiment, the signal processing section includes a complex digital signal channel select filter to select the signal channel and suppress the adjacent channel components. In other embodiments, the complex digital signal channel select filter selects the signal channel, shapes the selected signal channel to generate a shaped signal channel, and equalizes a group delay of the shaped signal channel.

Abstract: A fully-integrated tuner for performing signal channel selection and image rejection in an analog cable television system is provided. Various embodiments disclose a tuner including an analog RF section to process an analog RF input signal and generate complex low intermediate frequency digital signals, and a signal processing section configured to reduce image and signal leakage in the complex low intermediate frequency signals. The signal processing section selects a signal channel of the complex low intermediate frequency signals and suppresses channel components adjacent to the signal channel. In one embodiment, the signal processing section includes a complex digital signal channel select filter to select the signal channel and suppress the adjacent channel components. In other embodiments, the complex digital signal channel select filter selects the signal channel, shapes the selected signal channel to generate a shaped signal channel, and equalizes a group delay of the shaped signal channel.

Abstract: A fractional-N frequency synthesizer is based on a PLL which employs a multi-phase VCO and a multi-phase frequency divider to provide a desired fractional-N divider ratio. The multi-phase frequency divider includes a multi-modulus divider which divides a VCO output waveform with a division ratio that varies in response to a modulus control signal. The divided output is delayed to produce a plurality of outputs, each of which has a respective phase that corresponds with the phase of a respective VCO output. A phase selector provides a selected one of the outputs to the PLL's phase detector in response to a phase control signal such that the multi-phase frequency divider provides a fractional-N division ratio. To reduce fractional spurs, a modulator randomizes the modulus and phase control signals, which serves to randomize and thereby reduce phase mismatch error which might otherwise be present in the frequency synthesizer's output.