Abstract: A method of writing a magneto-resistive random access memory (MRAM) cell includes providing a writing pulse to write a value to the MRAM cell; and verifying a status of the MRAM cell immediately after the step of providing the first writing pulse. In the event of a write failure, the value is rewritten into the MRAM cell.

Abstract: A piezoelectric buzzer includes a housing unit, a buzzer unit, and first and second terminals. The housing unit includes first and second housings coupled together. The second housing includes a base plate and a pair of spaced apart insert seats, each of which protrudes inwardly from the base plate toward the first housing and is formed with an insert hole. The buzzer unit is disposed in the resonant chamber and includes a vibrating plate and a piezoelectric plate attached to the vibrating plate. The first and second terminals are inserted respectively into the insert holes of the insert seats, and have a respective connection section extending outwardly of the housing unit, and a respective extending section abutting against a respective one of the vibrating plate and the piezoelectric plate.

Abstract: A method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of memory cells includes: forming a fixed magnetic layer having magnetic moments fixed in a predetermined direction; forming a tunnel layer over the fixed magnetic layer; forming a free magnetic layer, having magnetic moments aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer; forming a hard mask on the free magnetic layer partially covering the free magnetic layer; and unmagnetizing portions of the free magnetic layer uncovered by the hard mask for defining one or more magnetic tunnel junction (MTJ) units.

Abstract: An integrated circuit structure includes a first fixed magnetic element; a second fixed magnetic element; and a composite free magnetic element between the first and the second fixed magnetic elements. The composite free magnetic element includes a first free layer and a second free layer.

Abstract: The present disclosure provides a multi-transistor element including a substrate, a first floating gate disposed on the substrate, a second floating gate disposed on the substrate and coupled to the first floating gate, and a first active region disposed in the substrate and coupled to the first and second floating gates.

Abstract: A conveying screw member for a plastic granule cutting and transporting mechanism includes a plastic granule collector, a heating conduit, a conveying screw, a plastic granule molding structure and a power transmission device. The plastic granule collector is a hollow cylinder which has an outlet being positioned thereon. The heating conduit is a longitudinal hollow tube which has a round hole being respectively positioned at both ends. The conveying screw member which has the conveying screw being set thereon, and the reversing screws and two supporting bases being respectively set at both ends is installed in the heating conduit. The plastic granule molding structure is equipped near the edge of the end of the heating conduit. The power transmission device is installed near the plastic granule collector and attached to the supporting base of one end of the conveying screw member.

Abstract: A MRAM cell structure includes a bottom electrode; a magnetic tunnel junction unit disposed on the bottom electrode; a top electrode disposed on the magnetic tunnel junction unit; and a blocking layer disposed on the top electrode, wherein the blocking layer is wider than the magnetic tunnel junction unit for preventing against formation of a short circuit between a contact and the magnetic tunnel junction unit.

Abstract: A method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of memory cells includes: forming a fixed magnetic layer having magnetic moments fixed in a predetermined direction; forming a tunnel layer over the fixed magnetic layer; forming a free magnetic layer, having magnetic moments aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer; forming a hard mask on the free magnetic layer partially covering the free magnetic layer; and unmagnetizing portions of the free magnetic layer uncovered by the hard mask for defining one or more magnetic tunnel junction (MTJ) units.

Abstract: A piezoelectric buzzer includes a housing unit, a buzzer unit, and first and second terminals. The housing unit includes first and second housings coupled together. The second housing includes a base plate and a pair of spaced apart insert seats, each of which protrudes inwardly from the base plate toward the first housing and is formed with an insert hole. The buzzer unit is disposed in the resonant chamber and includes a vibrating plate and a piezoelectric plate attached to the vibrating plate. The first and second terminals are inserted respectively into the insert holes of the insert seats, and have a respective connection section extending outwardly of the housing unit, and a respective extending section abutting against a respective one of the vibrating plate and the piezoelectric plate.

Abstract: A method for forming a double density wordline. A semiconductor substrate having a poly layer, a first insulating layer, a first dummy poly layer, and a second insulating layer is provided. The second insulating layer and the first dummy poly layer separated by an opening are a first wordline mask and a second wordline mask respectively. A spacer is formed on a sidewall of the opening, and the opening is filled with a second dummy poly layer. The spacer, the second insulating layer, and the exposed first insulating layer are removed to form a third wordline mask, the third wordline is composed of the second dummy poly layer and the unexposed first insulating layer. The poly layer is etched to form a first wordline, a second wordline, and a third wordline using the first wordline mask, the second wordline mask, and the third wordline mask as etching masks.

Abstract: A method for forming a double density wordline. A semiconductor substrate having a poly layer, a first insulating layer, a first dummy poly layer, and a second insulating layer is provided. The second insulating layer and the first dummy poly layer separated by an opening are a first wordline mask and a second wordline mask respectively. A spacer is formed on a sidewall of the opening, and the opening is filled with a second dummy poly layer. The spacer, the second insulating layer, and the exposed first insulating layer are removed to form a third wordline mask, the third wordline is composed of the second dummy poly layer and the unexposed first insulating layer. The poly layer is etched to form a first wordline, a second wordline, and a third wordline using the first wordline mask, the second wordline mask, and the third wordline mask as etching masks.

Abstract: A non-volatile memory device structure, having a plurality of gates, a plurality of bit lines and a plurality of word lines. The gates are formed in a substrate. The bit lines are between the gates and formed of a buried diffusion line and an elevated conductor layer formed on the buried diffusion line. The word lines are substantially perpendicular to the bit lines over the gates and across the elevated conductor layer of the bit lines. The sidewall of the elevated conductor layer of the bit lines further has a first spacer, while the sidewall of the word lines has a second spacer.

Abstract: A MROM memory cell structure for storing multi level bit information is disclosed. First of all, a substrate is provided. The substrate has first and second trenches therein, wherein the first trench is deeper than second trench. A conformnal dielectric layer formed on sidewall and bottom of the first and second trenches. A conductive layer filled in the first and second trenches and on the substrate. A first doped region is formed under the first trench. A second doped region is formed under the second trench. A third doped region is formed in surface of the substrate and between the first and second trenches.

Abstract: A method for forming cells array of mask read only memory, at least includes: form numerous gate structures on substrate; form numerous doped regions in uncovered part of substrate; form first conductor layer on uncovered part of substrate with a thickness essentially equal to thickness of gate structures; form first dielectric layer on first conductor layer; form second conductor layer on both gate structures and first dielectric layer; perform a pattern transform process for transferring both second conductor layer and gate structures into conductor lines as word lines; form second dielectric layer on sidewalls of conductor lines to form spacer; form code photoresist on second conductor layer; and perform ions implantation process for implant numerous ions into partial substrate which is not covered by code photoresist.

Abstract: The present invention provides a method of fabricating an optical fiber module. The optical fiber module includes an optical device and an optical fiber side connector for connecting with an optical fiber device. In the method of fabricating the optical fiber module, an optical device side connector with a protruding part at its connection surface is provided at first. Next, the optical device side connector is combined and fitted to the optical device, followed by aligning the optical device and the optical fiber side connector. Finally, an electric current is applied to the protruding part of the optical device side connector to weld the optical device side connector and the optical fiber side connector.

Abstract: A semiconductor substrate having a source/drain region is initially provided, wherein a channel is formed in the space between the source/drain region within the semiconductor substrate. Then the oxide-nitride-oxide layers are formed on the semiconductor substrate, wherein the nitride layer is a charge trapping layer. Afterward, an electrically conductive material layer such as a gate is formed on and overlays the oxide-nitride-oxide layers. Subsequently, the memory cell is programmed by ultraviolet light irradiation to increase the threshold voltage of the memory cell.

Abstract: A cells array of mask read only memory, at least includes numerous essentially parallel cells chains and numerous isolation dielectric layers which are located between any two adjacent cells chains. Each cells chain at least includes: numerous gates that located on a substrate, numerous doped regions, numerous polysilicon layers, numerous cover dielectric layers, a conductor layer and numerous isolation dielectric layers.

Abstract: A method for forming a non-volatile memory is disclosed. The invention uses elevated buried diffusion polysilicon layers (BDPOLY) and spacers to form self-aligned contact so that the process window can be upgraded. The spacers can be used as an etching stop layer so that the misalignment of contact holes will not present any process issues and device failures resulting from the etching of the contact holes.

Abstract: A method of fabricating a mask read only memory. Gate stacked structures, each of which made up of a gate dielectric layer, a gate conductive layer and a gate cap layer, are formed on a substrate. Source/drain regions are between, but not adjacent to the gate stacked structures. Regions between the source/drain regions and the gate stacked structures are coding areas. A dielectric layer is formed to fill spaces between the gate stacked structures. A photoresist layer with openings exposing the first dielectric layer on the coding areas is formed. The exposed first dielectric layer is removed to form implantation openings of the coding areas. Ion implantation is performed on the exposed coding areas. The photoresist layer is removed, and another dielectric layer is formed to fill the implantation openings. An etching back process is performed to expose the gate conductive layer. A word line is formed on the gate conductive layer.

Abstract: First of all, a semiconductor substrate having a source/drain region is provided, wherein a channel being formed in the space between the source/drain region within the semiconductor substrate. Then the oxide-nitride-oxide layers are formed on the semiconductor substrate, wherein the nitride layer is a charge trapping layer. Afterward, an electrically conductive material layer as a gate is formed on and overlaying the oxide-nitride-oxide layers. Subsequently, the memory cell is programmed by ultraviolet light irradiation to increase threshold voltage of the memory cell.