Patents by Inventor Chun-Jung Tang

Chun-Jung Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11227769
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate; forming an inter-metal dielectric (IMD) layer on the metal gate; forming a metal interconnection in the IMD layer; and performing a high pressure anneal (HPA) process for improving work function variation of the metal gate.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: January 18, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Jung Tang, Yu-Jen Liu
  • Publication number: 20210272813
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate; forming an inter-metal dielectric (IMD) layer on the metal gate; forming a metal interconnection in the IMD layer; and performing a high pressure anneal (HPA) process for improving work function variation of the metal gate.
    Type: Application
    Filed: March 30, 2020
    Publication date: September 2, 2021
    Inventors: Chun-Jung Tang, Yu-Jen Liu
  • Patent number: 10347761
    Abstract: A tunnel field effect transistor (TFET) includes: a first gate structure on a substrate; a source region having a first conductive type on one side of the first gate structure; a drain region having a second conductive type on another side of the first gate structure; a first isolation structure adjacent to the source region; and a second isolation structure adjacent to the drain region. Preferably, the first isolation and the second isolation comprise different material and different depths or same material and different depths.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: July 9, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hao Lin, Chun-Jung Tang, Hsin-Yu Chen, Shou-Wei Hsieh
  • Publication number: 20190131453
    Abstract: A tunnel field effect transistor (TFET) includes: a first gate structure on a substrate; a source region having a first conductive type on one side of the first gate structure; a drain region having a second conductive type on another side of the first gate structure; a first isolation structure adjacent to the source region; and a second isolation structure adjacent to the drain region. Preferably, the first isolation and the second isolation comprise different material and different depths or same material and different depths.
    Type: Application
    Filed: November 24, 2017
    Publication date: May 2, 2019
    Inventors: Chun-Hao Lin, Chun-Jung Tang, Hsin-Yu Chen, Shou-Wei Hsieh
  • Patent number: 9741830
    Abstract: The present invention provides a method of forming a metal oxide semiconductor (MOS) device comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and a part thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: August 22, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
  • Publication number: 20160225880
    Abstract: The present invention provides a method of forming a metal oxide semiconductor (MOS) device comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and a part thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Application
    Filed: April 7, 2016
    Publication date: August 4, 2016
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
  • Publication number: 20160155837
    Abstract: The present invention provides a metal oxide semiconductor (MOS) device, comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and apart thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Application
    Filed: December 27, 2014
    Publication date: June 2, 2016
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
  • Patent number: 9337339
    Abstract: The present invention provides a metal oxide semiconductor (MOS) device, comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and apart thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: May 10, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen