Patents by Inventor Chun Liu

Chun Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240074962
    Abstract: A dry formulation useful to prepare a hair care product is provided. The formulation comprises: i) a water soluble film-forming polymer; ii) at least one hair product ingredient, and iii) optionally, a pH adjuster in an amount sufficient to establish a pH in the range of about 3.0 to about 7.5. The dry formulation may be further processed, for example, prepared into tablets or other dosage forms, for ease of use. Methods of making the hair care product are also provided, as well as kits containing the formulation.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 7, 2024
    Inventor: Ying Chun Liu
  • Patent number: 11923237
    Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
  • Patent number: 11923886
    Abstract: An antenna device and a method for configuring the same are provided. The antenna device includes a grounding metal, a grounding part, a radiating part, a feeding part, a proximity sensor, and a sensing metal. The radiating part is electrically connected to the grounding metal through the grounding part. The feeding part is coupled to the grounding metal through a feeding point. The sensing metal is electrically connected to the proximity sensor. The sensing metal is separated from the radiating part at a distance. The distance is less than or equal to one thousandth of a wavelength corresponding to an operating frequency of the antenna device.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: March 5, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Jhih-Ciang Chen, Shih-Chia Liu, Yen-Hao Yu, Li-Chun Lee, Yan-Ming Lin, Jui-Hung Lai
  • Patent number: 11921001
    Abstract: A method and system for inspecting deviation in dynamic characteristics of a feeding system are provided, and the method includes: exciting the feeding system and detecting vibrations of a subcomponent of a component to be inspected of the feeding system to generate a monitoring excitation signal in a monitoring mode; calculating, by a modal analysis method, monitoring eigenvalues and monitoring eigenvectors of the monitoring excitation signal; determining, by a modal verification method, similarity between the monitoring eigenvalues and standard eigenvalues of a digital twin model and similarity between the monitoring eigenvectors and standard eigenvectors of the digital twin model; determining that the dynamic characteristics of the subcomponent are deviated, when the monitoring eigenvalues and monitoring eigenvectors are not similar to the standard eigenvalues and standard eigenvectors. Therefore, the subcomponent whose dynamic characteristics are deviated can be sensed remotely and precisely.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: March 5, 2024
    Assignee: Hiwin Technologies Corp.
    Inventors: Hsien-Yu Chen, Yu-Sheng Chiu, Chih-Chun Cheng, Wen-Nan Cheng, Chi-Ming Liu
  • Patent number: 11919997
    Abstract: A white photosensitive resin composition, a white spacer, a light conversion layer, and a light-emitting device are provided. The white photosensitive resin composition includes a polymerizable compound (A), an alkali-soluble resin (B), a photopolymerization initiator (C), a solvent (D), and a white pigment (E). The polymerizable compound (A) includes an ethylenically-unsaturated monomer (A-1) represented by formula (I-1) and a thiol compound (A-2) having two or more thiol groups in one molecule, wherein based on 100 mass % of the polymerizable compound (A), a total content of the ethylenically-unsaturated monomer (A-1) and the thiol compound (A-2) is 10 mass % to 98 mass %.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: March 5, 2024
    Assignee: eChem Solutions Corp.
    Inventors: Meng-Po Liu, Yu-Chun Chen
  • Publication number: 20240072459
    Abstract: An electrical connection structure including a first substrate, a first conductive pad, a second substrate, a second conductive pad, at least two through holes and a conductive material. The first conductive pad is disposed on the first substrate and includes a first top surface. The second conductive pad is disposed on the second substrate and includes a second top surface. The at least two through holes pass through the first substrate and expose portions of the second top surface. A portion of the conductive material is disposed within the at least two through holes, and the conductive material electrically connects the first conductive pad and the second conductive pad.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 29, 2024
    Applicant: InnoLux Corporation
    Inventors: Chia-Chun LIU, Hao-Jung HUANG
  • Publication number: 20240069606
    Abstract: A portable electronic device including a first body, a second body, and a hinge mechanism is provided. The second body is connected to the first body through the hinge mechanism, and the hinge mechanism has a basis axis located at the first body and a rotation axis located at a lower end of the second body. When the second body rotates with respect to the first body, the rotation axis slides along an arc shaped path with respect to the basis axis to increase or decrease a distance between the rotation axis and the basis axis and increase or decrease a distance between the lower end of the second body and a back end of the first body.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 29, 2024
    Applicants: Acer Incorporated, Sinher Technology Inc.
    Inventors: Yi-Ta Huang, Cheng-Nan Ling, Chih-Chun Liu, Yung-Chang Chiang
  • Publication number: 20240071854
    Abstract: Some implementations described herein a provide a multi-die package and methods of formation. The multi-die package includes a dynamic random access memory integrated circuit die over a system-on-chip integrated circuit die, and a heat transfer component between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, which may correspond to a dome-shaped structure, may be on a surface of the system-on-chip integrated circuit die and enveloped by an underfill material between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, in combination with the underfill material, may be a portion of a thermal circuit having one or more thermal conductivity properties to quickly spread and transfer heat within the multi-die package so that a temperature of the system-on-chip integrated circuit die satisfies a threshold.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Wen-Yi LIN, Kuang-Chun LEE, Chien-Chen LI, Chien-Li KUO, Kuo-Chio LIU
  • Publication number: 20240068119
    Abstract: A casing structure of electronic device including a metal base plate, a transparent cathodic electrodeposition paints layer, and a transparent paints coating layer is provided. The metal base plate has brushed texture and high gloss surface. The transparent cathodic electrodeposition paints layer is disposed on the base metal base plate. The transparent paints coating layer is disposed on the transparent cathodic electrodeposition paints layer. A manufacturing method of casing structure of electronic device is also provided.
    Type: Application
    Filed: March 2, 2023
    Publication date: February 29, 2024
    Applicant: Acer Incorporated
    Inventors: Tzu-Wei Lin, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai
  • Publication number: 20240071504
    Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Chun LIAO, Yu-Kai CHANG, Yi-Ching LIU, Yu-Ming LIN, Yih WANG, Chieh LEE
  • Publication number: 20240072128
    Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Inventors: Tsan-Chun Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240067746
    Abstract: Disclosed herein are humanized antibodies, antigen-binding fragments thereof, and antibody conjugates, that are capable of specifically binding to certain biantennary Lewis antigens, which antigens are expressed in a variety of cancers. The presently disclosed antibodies are useful to target antigen-expressing cells for treatment or detection of disease, including various cancers. Also provided are polynucleotides, vectors, and host cells for producing the disclosed antibodies and antigen-binding fragments thereof. Pharmaceutical compositions, methods of treatment and detection, and uses of the antibodies, antigen-binding fragments, antibody conjugates, and compositions are also provided.
    Type: Application
    Filed: February 28, 2023
    Publication date: February 29, 2024
    Inventors: Tong-Hsuan CHANG, Mei-Chun YANG, Liahng-Yirn LIU, Jerry TING, Shu-Yen CHANG, Yen-Ying CHEN, Yu-Yu LIN, Shu-Lun TANG
  • Publication number: 20240071950
    Abstract: Integrated circuit packages and methods of forming the same are discussed. In an embodiment, a device includes: a package substrate; a semiconductor device attached to the package substrate; an underfill between the semiconductor device and the package substrate; and a package stiffener attached to the package substrate, the package stiffener includes: a main body extending around the semiconductor device and the underfill in a top-down view, the main body having a first coefficient of thermal expansion; and pillars in the main body, each of the pillars extending from a top surface of the main body to a bottom surface of the main body, each of the pillars physically contacting the main body, the pillars having a second coefficient of thermal expansion, the second coefficient of thermal expansion being less than the first coefficient of thermal expansion.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: Wen-Yi Lin, Kuang-Chun Lee, Chien-Chen Li, Chien-Li Kuo, Kuo-Chio Liu
  • Patent number: 11913084
    Abstract: A quenching fixture adapted to clamp at least one workpiece is provided. The quenching fixture includes a first positioning component and a second positioning component. Both of the first positioning component and the second positioning component have a positioning surface, multiple protrusions protruding from the positioning surface and a heat dissipation channel disposed between the protrusions in a staggered manner. The positioning surface of the first positioning component faces the positioning surface of the second positioning component, and the protrusions of the first positioning component overlap the protrusions of the second positioning component. The workpiece is clamped between the protrusions of the first positioning component and the protrusions of the second positioning component.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: February 27, 2024
    Assignee: Acer Incorporated
    Inventors: Yi-Ta Huang, Cheng-Nan Ling, Chih-Chun Liu
  • Patent number: 11916077
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Patent number: 11908900
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • Patent number: 11901323
    Abstract: A semiconductor package includes a first device, a second device and a solder region. The first device includes a first conductive pillar, wherein the first conductive pillar has a first sidewall, a second sidewall opposite to the first sidewall, a first surface and a second surface physically connected to the first surface, the first surface and the second surface are disposed between the first sidewall and the second sidewall, and an included angle is formed between the first surface and the second surface. The solder region is disposed between the first conductive pillar and the second device to bond the first device and the second device.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiang-Jui Chu, Ching-Wen Hsiao, Hao-Chun Liu, Ming-Da Cheng, Young-Hwa Wu, Tao-Sheng Chang
  • Patent number: 11894481
    Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body having a topmost surface; a first light-emitting device disposed on the carrier body and having a light-emitting surface; and a light-receiving device comprising a group III-V semiconductor material disposed on the carrier body and having a light-receiving surface. The light-emitting surface is separated from the topmost surface by first distant H1, the light-receiving surface is separated from the topmost surface by a second distance H2, and H1 is different from H2.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: February 6, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Yi-Chieh Lin, Shiuan-Leh Lin, Yung-Fu Chang, Shih-Chang Lee, Chia-Liang Hsu, Yi Hsiao, Wen-Luh Liao, Hong-Chi Shih, Mei-Chun Liu
  • Publication number: 20240036728
    Abstract: Methods and apparatuses for processing data are provided. In an implementation, a method comprising: obtaining, by a reduction server of a plurality of reduction servers in a distributed processing system and from a first storage area, metadata of first data to be read, wherein the first data comprises a target data block in a plurality of data blocks of second data, and wherein the second data comprises a processing result of a mapping server of a plurality of mapping servers for input data, determining a first address of the first data in a global memory based on the metadata, wherein the global memory comprises memories of the plurality of mapping servers and the plurality of reduction servers, and reading the first data from the global memory based on the first address.
    Type: Application
    Filed: October 12, 2023
    Publication date: February 1, 2024
    Inventors: Hua XU, Xiaoming BAO, Hongwei SUN, Yihai ZHENG, Chun LIU
  • Patent number: D1016601
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: March 5, 2024
    Inventor: Yu-Chun Liu