Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips stacked in a multi-layer structure; a correction circuit in each semiconductor chip configured to reflect a delay time corresponding to the position of the chip in the stack into an input signal to output to each semiconductor chip; and a plurality of through-chip vias formed vertically through each of the semiconductor chips and configured to transmit the input signal to the semiconductor chip.

Abstract: Provided is a stacked memory device including a base die and a plurality of core dies. The base die may include: a weak cell address storage unit for storing weak cell addresses; a serialization unit for selecting at least one of the weak cell addresses as a target weak cell address, converting the selected target weak cell address into a serial weak cell address, and outputting a strobe signal synchronized with the serial weak cell address; a deserialization unit for storing the serial weak cell address based on the strobe signal, and converting the stored address into a parallel weak cell address based on a refresh end signal; and a refresh control unit for selecting the parallel weak cell address or a refresh address generated based on a refresh signal, and outputting a target address.

Abstract: An embodiment may include a first replica driver group configured for replicating an output driver of a physical area. A second replica driver group configured for replicating an output driver of a test electrode area for direct access of a memory, and an impedance calibration unit configured to independently perform an impedance matching operation of the first replica driver group and the second replica driver group.

Abstract: A memory device includes a memory array suitable for storing write data of the memory device and providing the stored data as read data of the memory device, a programmable storage unit suitable for storing information for the memory device, a command decoder suitable for storing decoding one or more command signals, and generating a write command for writing the write data, a read command for outputting the read data, and an information read command for outputting information stored in the programmable storage unit, a control unit suitable for controlling the information stored in the programmable storage unit to be sequentially read in response to activation of the information read command, and an output unit suitable for outputting the read information to an outside of the memory device in response to the information read command.

Abstract: A semiconductor apparatus includes a command decoding unit configured to decode an internal command, an internal clock and an internal clock enable signal, and generate an internal control signal; a clock enable signal control unit configured to receive a pre-clock enable signal and output one of the pre-clock enable signal and an enabled internal clock enable signal as the internal clock enable signal in response to a first test signal; an enable signal selection unit configured to output one of the pre-clock enable signal and a second to test signal as a counting enable signal in response to the first test signal; and a counting unit configured to perform a counting operation during an enable period of the counting enable signal, and output a counting code.

Abstract: A semiconductor apparatus includes a direct access section, an interface section, and a through-silicon via region. The direct access section receives a normal clock, a first clock, and a control signal through a direct access pad. The interface section comprises a plurality of channel circuits suitable for aligning the control signal to the first clock, and outputting an aligned control signal. The through-silicon via region transfers the normal clock and the aligned control signal from the interface section to a plurality of channels corresponding to the respective channel circuits.

Abstract: A semiconductor memory device includes a row input section suitable for receiving a first row signal including a first row command and a first row address, corresponding to an active command, during a test operation of the active command, a column input section suitable for receiving a second row signal including a second row address corresponding to the active command during the test operation of the active command, and a signal control section suitable for generating an internal row signal for an operation of the active command by transforming the first row signal and the second row signal outputted from the row input section and the column input section.

Abstract: A multi-chip package system includes a signal transmission line commonly coupled to a plurality of semiconductor chips to transfer data to/from the semiconductor chips from/to outside; and a termination controller suitable for detecting a loading value of the signal transmission line and controlling a termination operation on the signal transmission line based on the loading value.

Abstract: An integrated circuit may include a nonvolatile memory circuit, a data bus suitable for transferring data outputted from the nonvolatile memory circuit, a shift register suitable for sequentially activating first to Nth selection signals whenever a clock is activated, and first to Nth latch circuits corresponding to the first to Nth selection signals, respectively, and suitable for storing data of the data bus in response to activation of one or more of the first to Nth selection signals.

Abstract: A phase detector includes a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal, a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal, and an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to a control signal.

Abstract: A semiconductor apparatus includes a command decoding unit configured to decode an internal command, an internal clock and an internal clock enable signal, and generate an internal control signal; a clock enable signal control unit configured to receive a pre-clock enable signal and output one of the pre-clock enable signal and an enabled internal clock enable signal as the internal clock enable signal in response to a first test signal; an enable signal selection unit configured to output one of the pre-clock enable signal and a second to test signal as a counting enable signal in response to the first test signal; and a counting unit configured to perform a counting operation during an enable period of the counting enable signal, and output a counting code.

Abstract: An embodiment may include a first replica driver group configured for replicating an output driver of a physical area. A second replica driver group configured for replicating an output driver of a test electrode area for direct access of a memory, and an impedance calibration unit configured to independently perform an impedance matching operation of the first replica driver group and the second replica driver group.

Abstract: A multi-chip package system includes a signal transmission line commonly coupled to a plurality of semiconductor chips to transfer data to/from the semiconductor chips from/to outside; and a termination controller suitable for detecting a loading value of the signal transmission line and controlling a termination operation on the signal transmission line based on the loading value.

Abstract: A semiconductor apparatus includes a TSV formed to be electrically connected with another chip and a TSV test unit configured to check a capacitance component of the TSV to generate a TSV abnormality signal.

Abstract: A semiconductor apparatus includes a direct access section, an interface section, and a through-silicon via region. The direct access section receives a normal clock, a first clock, and a control signal through a direct access pad. The interface section comprises a plurality of channel circuits suitable for aligning the control signal to the first clock, and outputting an aligned control signal. The through-silicon via region transfers the normal clock and the aligned control signal from the interface section to a plurality of channels corresponding to the respective channel circuits.

Abstract: A semiconductor apparatus includes a direct access section, an interface section, and a through-via region. The direct access section receives first and second groups of input signals through a direct access pad, and generates first and second groups of control signals based on the first and second groups of input signals. The interface section comprises a plurality of channel circuits suitable for receiving a part or all of the first and second groups of control signals in response to a plurality of channel selection signals. The through-via region electrically couples the plurality of channel circuits and a plurality of stack dies to form a plurality of channels, respectively.

Abstract: A semiconductor memory device includes a row input section suitable for receiving a first row signal including a first row command and a first row address, corresponding to an active command, during a test operation of the active command, a column input section suitable for receiving a second row signal including a second row address corresponding to the active command during the test operation of the active command, and a signal control section suitable for generating an internal row signal for an operation of the active command by transforming the first row signal and the second row signal outputted from the row input section and the column input section.

Abstract: A semiconductor device includes a plurality of stacked chips, a reference through silicon via (TSV) set passing through the plurality of stacked chips, a plurality of TSVs passing through the plurality of stacked chips, a reference delay information generation unit suitable for generating a reference delay information indicating an amount of delay of the reference TSV set and a determination unit suitable for determining abnormality of the plurality of TSVs by comparing a first test signal with each of a plurality of second test signals, wherein the first test signal is an initial test signal delayed by an amount of delay corresponding to the reference delay information, and wherein each of the plurality of second test signals is the initial test signal delayed by corresponding one of the plurality of TSVs.

Abstract: A semiconductor memory device includes an operation control block suitable for controlling an entrance/escape to/from a test public mode and a test application mode in response to a first preset command and an address signal that is inputted through an address pad, a test normal input block suitable for receiving the address signal as a test operation signal in response to the first preset command in the test application mode, a test public input block suitable for receiving a data signal, which is inputted through a data pad as the test operation signal in response to a second preset command in the test public mode, and an internal circuit suitable for performing a preset test operation in response to the test operation signal in the test application mode.

Abstract: An integrated circuit may include a nonvolatile memory circuit, a data bus suitable for transferring data outputted from the nonvolatile memory circuit, a shift register suitable for sequentially activating first to Nth selection signals whenever a clock is activated, and first to Nth latch circuits corresponding to the first to Nth selection signals, respectively, and suitable for storing data of the data bus in response to activation of one or more of the first to Nth selection signals.