Patents by Inventor Chun-Sheng Liang

Chun-Sheng Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240243192
    Abstract: A semiconductor device structure includes a dielectric wall disposed over a substrate, a plurality of first semiconductor layers vertically stacked and extended outwardly from a first side of the dielectric wall, a plurality of second semiconductor layers vertically stacked and extended outwardly from a second side of the dielectric wall, a first epitaxial source/drain (S/D) feature disposed on the first side of the dielectric wall, a second epitaxial S/D feature disposed on the second side of the dielectric wall, a first bottom dielectric layer extended outwardly from the first side of the dielectric wall, and a second bottom dielectric layer extended outwardly from the second side of the dielectric wall.
    Type: Application
    Filed: January 12, 2023
    Publication date: July 18, 2024
    Inventors: Ming-Heng TSAI, Chun-Sheng LIANG, Ta-Chun LIN, JHON JHY LIAW
  • Patent number: 12040237
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a spacer over a side of the gate stack. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a first recess, the dielectric layer has an upper portion and a first lower portion, the upper portion is over the first recess, the first recess is between the first lower portion and the spacer, and the upper portion has a convex curved sidewall.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Heng Tsai, Chun-Sheng Liang, Pei-Lin Wu, Yi-Ren Chen, Shih-Hsun Chang
  • Publication number: 20240224486
    Abstract: A device includes a first transistor, a second transistor, and a dielectric wall. The first transistor includes first semiconductor channel layers, a first gate structure, and first source/drain structures on opposite sides of the first gate structure. The second transistor includes second semiconductor channel layers, a second gate structure, and second source/drain structures on opposite sides of the second gate structure. The dielectric wall includes a first sidewall abutting side surfaces of the first semiconductor channel layers in a first cross-sectional view taken along a longitudinal axis of the first gate structure, the first sidewall of the dielectric wall also abutting side surfaces of second semiconductor channel layers in a second cross-sectional view taken along a longitudinal axis of the second gate structure, in which in a top view, the first sidewall of the dielectric wall has a stepped profile.
    Type: Application
    Filed: January 3, 2023
    Publication date: July 4, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Heng TSAI, Chun-Sheng LIANG, Ta-Chun LIN, Jhon Jhy LIAW
  • Publication number: 20240222431
    Abstract: A method of forming a semiconductor device includes the following steps. A substrate is patterned to form a fin structure. The fin structure is recessed to form a recess in the fin structure. An epitaxial source/drain region is grown from the recess. A first silicide layer is formed on the epitaxial source/drain region. A first portion of the first silicide layer is thinned, while leaving a second portion of the first silicide layer un-thinned. A metal contact is formed in contact with the thinned first portion of the first silicide layer.
    Type: Application
    Filed: January 3, 2023
    Publication date: July 4, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Yi-Hsien CHEN, Chi HUANG, Chih-Pin TSAO, Chun-Sheng LIANG, Chih-Hao CHANG
  • Publication number: 20240222430
    Abstract: A semiconductor device includes a dielectric wall, an isolation structure, first and second semiconductor channels, and a gate structure. The dielectric wall is on a substrate and extending along a first direction from a top view. The isolation structure is in the substrate and having a top surface lower than that of the dielectric wall. The first and second semiconductor channels are respectively on opposite first and second sides of the dielectric wall. The gate structure extends across the first and second semiconductor channels along a second direction different from the first direction from the top view. From the top view the gate structure comprises a first profile over the first semiconductor channels and a second profile over the isolation structure, the first profile has a first width at the first side of the dielectric wall, and the first width is greater than a width of the second profile.
    Type: Application
    Filed: January 3, 2023
    Publication date: July 4, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huang-Chao CHANG, Ta-Chun LIN, Chun-Sheng LIANG, Jhon Jhy LIAW
  • Patent number: 12027415
    Abstract: In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Ju-Li Huang, Chun-Sheng Liang, Jeng-Ya Yeh
  • Patent number: 12015077
    Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ju-Li Huang, Chun-Sheng Liang, Ming-Chi Huang, Ming-Hsi Yeh, Ying-Liang Chuang, Hsin-Che Chiang
  • Publication number: 20240178128
    Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall. The structure also includes a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type. The structure further includes a gate bridge contact disposed on the first dielectric wall, and a gate via contact disposed on the gate bridge contact.
    Type: Application
    Filed: January 22, 2023
    Publication date: May 30, 2024
    Inventors: Hong-Chih CHEN, Chun-Sheng LIANG, Yu-San CHIEN, Wei-Chih KAO
  • Publication number: 20240170533
    Abstract: A semiconductor structure includes a first device unit and a second device unit, each of which includes channel features spaced apart from each other, and a dielectric wall disposed between the first and second device units. The dielectric wall includes a first part which includes a plurality of first portions that are in direct contact with the channel features of the first device unit, and a second part which includes a plurality of second portions that are in direct contact with the channel features of the second device unit. At least one of the first and second parts carries positive or negative charges.
    Type: Application
    Filed: February 22, 2023
    Publication date: May 23, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Han TSAI, Ta-Chun LIN, Chun-Sheng LIANG, Chih-Hao CHANG
  • Publication number: 20240162308
    Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.
    Type: Application
    Filed: February 9, 2023
    Publication date: May 16, 2024
    Inventors: Pin Chun SHEN, Che Chia CHANG, Li-Ying WU, Jen-Hsiang LU, Wen-Chiang HONG, Chun-Wing YEUNG, Ta-Chun LIN, Chun-Sheng LIANG, Shih-Hsun CHANG, Chih-Hao CHANG, Yi-Hsien CHEN
  • Publication number: 20240162336
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first stack structure extends above the isolation structure, and the first stack structure includes a plurality of first nanostructures along a first direction. The semiconductor structure also includes a second stack structure formed adjacent to the first stack structure, and the second stack structure includes a plurality of second nanostructures along the first direction. A first dielectric wall between the first stack structure and the second stack structure, and the first dielectric wall is directly over a first portion of the isolation structure and surrounded by a second portion of the isolation structure, and a top surface of the first portion of the isolation structure is lower than a top surface of the second portion of the isolation structure.
    Type: Application
    Filed: March 8, 2023
    Publication date: May 16, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Heng TSAI, Chun-Sheng LIANG
  • Publication number: 20240162321
    Abstract: A semiconductor structure includes a substrate, a dielectric wall, and two device units. The dielectric wall has two side surfaces opposite to each other. The two device units are respectively formed at the two side surfaces of the dielectric wall. Each of the device units includes channel features, a gate feature and a dielectric filler unit. The channel features are disposed on a corresponding one of the side surfaces of the dielectric wall, and spaced apart from each other. The gate feature is formed around the channel features and disposed on the corresponding one of the side surfaces of the dielectric wall. The dielectric filler unit includes a plurality of first dielectric fillers, each of which is disposed between the dielectric wall and a corresponding one of the channel features. The first dielectric fillers have a dielectric constant greater than that of the dielectric wall.
    Type: Application
    Filed: February 22, 2023
    Publication date: May 16, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huang-Chao CHANG, Ta-Chun LIN, Chun-Sheng LIANG, Jhon-Jhy LIAW
  • Publication number: 20240145555
    Abstract: Semiconductor structures and processes are provided. A semiconductor structure of the present disclosure includes a first base portion and a second base portion extending lengthwise along a first direction, a first source/drain feature disposed over the first base portion, a second source/drain feature disposed over the second base portion, a center dielectric fin sandwiched between the first source/drain feature and the second source/drain feature along a second direction perpendicular to the first direction, and a source/drain contact disposed over the first source/drain feature, the second source/drain feature and the center dielectric fin. A portion of the source/drain contact extends between the first source/drain feature and the second source/drain feature along the second direction.
    Type: Application
    Filed: January 10, 2023
    Publication date: May 2, 2024
    Inventors: Ming-Heng Tsai, Chih-Hao Chang, Chun-Sheng Liang, Ta-Chun Lin
  • Publication number: 20240147685
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain (S/D) epitaxial feature disposed over a substrate, a second S/D epitaxial feature adjacent the first S/D epitaxial feature, and a hybrid fin disposed between the first and second S/D epitaxial features. The hybrid fin includes a first dielectric material, a second dielectric material disposed on the first dielectric material, a dielectric layer surrounding the first and second dielectric materials, and a high-k dielectric layer disposed in the first and second dielectric materials. The high-k dielectric layer has an upper surface located at a level between a level of an upper surface of the second dielectric material and a level of a lower surface of the second dielectric material.
    Type: Application
    Filed: January 19, 2023
    Publication date: May 2, 2024
    Inventors: Wen-Li Chiu, Chun-Sheng Liang
  • Publication number: 20240128267
    Abstract: A semiconductor device includes a first semiconductor structure, a second semiconductor structure, a first isolation block and a second isolation block. The first semiconductor structure includes a first gate structure wrapping around a first sheet structures and a second sheet structures, and a first dielectric wall disposed between and separating the first and second sheet structures. The second semiconductor structure includes a second gate structure wrapping around third sheet structures. The first isolation block is disposed on the first dielectric wall of the first semiconductor structure and separates the first gate structure into a first gate portion wrapping around the first sheet structures and a second gate portion wrapping around the second sheet structures. The second isolation block is disposed between the first and second semiconductor structures and separates the first gate structure from the second gate structure.
    Type: Application
    Filed: January 30, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Sheng Liang, Yu-San Chien, Pin Chun Shen, Wen-Chiang Hong, Chun-Wing Yeung
  • Publication number: 20240120337
    Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.
    Type: Application
    Filed: January 15, 2023
    Publication date: April 11, 2024
    Inventors: Ta-Chun LIN, Chih-Hung HSIEH, Chun-Sheng LIANG, Wen-Chiang HONG, Chun-Wing YEUNG, Kuo-Hua PAN, Chih-Hao CHANG, Jhon Jhy LIAW
  • Publication number: 20240113165
    Abstract: A semiconductor device includes a substrate, a first stack of semiconductor nanosheets, a second stack of semiconductor nanosheets, a gate structure and a first dielectric wall. The substrate includes a first fin and a second fin. The first stack of semiconductor nanosheets is disposed on the first fin. The second stack of semiconductor nanosheets is disposed on the second fin. The gate structure wraps the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall is disposed between the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall includes at least one neck portion between adjacent two semiconductor nanosheets of the first stack.
    Type: Application
    Filed: January 10, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun LIN, Chun-Sheng Liang, Chih-Hao Chang, Jhon Jhy Liaw
  • Publication number: 20240105786
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain (S/D) region disposed over a substrate, a second S/D region disposed over the substrate, a dielectric wall disposed between the first and second S/D regions, a first conductive contact disposed over and electrically connected to the first S/D region, a second conductive contact disposed over and electrically connected to the second S/D region, and a first dielectric material in contact with the dielectric wall. The first dielectric material has a top surface located at a first level between a top surface of the first conductive contact and a bottom surface of the first conductive contact, and the first dielectric material extends from the first level to a second level located below the bottom surface of the first conductive contact.
    Type: Application
    Filed: January 15, 2023
    Publication date: March 28, 2024
    Inventors: Chun-Sheng LIANG, Hong-Chih CHEN
  • Publication number: 20240105805
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes channel structures vertically stacked over a substrate and a source/drain structure laterally attached to the channel structures in the first direction. The semiconductor structure also includes a dielectric wall structure laterally attached to the channel structures in the second direction. The second direction is different from the first direction. In addition, the dielectric wall structure includes a bottom portion and a cap layer formed over the bottom portion. The semiconductor structure also includes an isolation feature vertically overlapping the cap layer of the dielectric wall structure and a gate structure formed around the channel structures and covering a sidewall of the isolation feature.
    Type: Application
    Filed: February 2, 2023
    Publication date: March 28, 2024
    Inventors: Chun-Sheng LIANG, Hong-Chih CHEN, Ta-Chun LIN, Shih-Hsun CHANG, Chih-Hao CHANG
  • Publication number: 20240088278
    Abstract: A semiconductor structure includes spaced apart first and second fins over a substrate, a separating wall over the substrate and having opposite first and second wall surfaces, multiple first channel features extending away from the first wall surface over the first fin such that the first channel features are spaced apart, multiple second channel features extending away from the second wall surface over the second fin such that the second channel features are spaced apart, two spaced apart first epitaxial structures on the first fin such that each first channel feature interconnects the first epitaxial structures, two spaced apart second epitaxial structures on the second fin such that each second channel feature interconnects the second epitaxial structures, and a dielectric structure including at least one bottom dielectric portion separating at least one of the first and second epitaxial structures from a corresponding first and second fins.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Chun-Sheng LIANG, Chun-Wing YEUNG, Chih-Hao CHANG