Abstract: A buffer circuit and a multiplexer using the buffer are provided. The buffer may selectively operate at a first mode or a second mode. The buffer includes a first signal input terminal, a first signal output terminal, and a path circuit coupled between the first signal input terminal and the first signal output terminal. The path circuit has a voltage source terminal. In response to the buffer operating at the first mode, a first signal transmission path is formed in the path circuit and between the first signal input terminal and the first signal output terminal. The first signal transmission path is disconnected from the voltage source terminal.

Abstract: The present invention relates to a coral composite extract, a composition including the same and a method of producing the same. The coral composite extract includes at least two briarane-type diterpenoid compounds from corals of Briareum violaceum, B. excavatum and B. stechei, thereby being applied as an effective ingredient of a skin external use composition, a cosmetic composition and a medicinal composition.

Abstract: A semiconductor memory device includes a substrate; a control gate disposed on the substrate; a source diffusion region disposed in the substrate and on a first side of the control gate; a select gate disposed on the source diffusion region, wherein the select gate has a recessed top surface; a charge storage structure disposed under the control gate; a first spacer disposed between the select gate and the control gate and between the charge storage structure and the select gate; a wordline gate disposed on a second side of the control gate opposite to the select gate; a second spacer between the wordline gate and the control gate; and a drain diffusion region disposed in the substrate and adjacent to the wordline gate.

Abstract: The present disclosure relates to a thermoplastic resin composition and an exterior material including the same. The thermoplastic resin composition included 90 to 99.5% by weight of styrene-based resins each including 5 to 30% by weight of acrylate rubber having a DLS average particle diameter of 0.25 to 0.32 ?m or a TEM average particle diameter of 0.2 to 0.27 ?m based on a total weight of the styrene-based resins; and 0.5 to 10% by weight of a polyamide resin, and an exterior material including the thermoplastic resin composition. According to the present disclosure, a low-gloss thermoplastic resin composition having excellent aesthetics, such as softness, luxuriousness, and naturalness, due to uniformity, low gloss, and improvement in surface texture while having mechanical properties and processability equal or superior to those of conventional ASA resins; and an exterior material including the low-gloss thermoplastic resin composition may be provided.

Abstract: A blood pressure detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a gas-pressure-sensing element, a driving-chip element, an encapsulation layer and a valve layer. The substrate includes inlet apertures. The microelectromechanical element and the gas-pressure-sensing element are stacked and integrally formed on the substrate. The encapsulation layer is encapsulated and positioned on the substrate. A flowing-channel space is formed above the microelectromechanical element and the gas-pressure-sensing element. The encapsulation layer includes an outlet aperture in communication with an airbag. The driving-chip element controls the microelectromechanical element, the gas-pressure-sensing element and valve units to transport gas.

Abstract: Techniques pertaining to seamless switching control for foldable or flip devices are described. A processor implemented in a multi-display apparatus having a primary display and a secondary display executes a status change with respect to the primary display and the secondary display by: (1) maintaining a power supplied to the secondary display during the status change; and (2) switching the primary display and the secondary display from a first state to a second state.

Abstract: Behavior report generation monitors the behavior of unknown sample files executing in a sandbox. Behaviors are encoded and feature vectors created based upon a q-gram for each sample. Prototypes extraction includes extracting prototypes from the training set of feature vectors using a clustering algorithm. Once prototypes are identified in this training process, the prototypes with unknown labels are reviewed by domain experts who add a label to each prototype. A K-Nearest Neighbor Graph is used to merge prototypes into fewer prototypes without using a fixed distance threshold and then assigning a malware family name to each remaining prototype. An input unknown sample can be classified using the remaining prototypes and using a fixed distance. For the case that no such prototype is close enough, the behavior report of a sample is rejected and tagged as an unknown sample or that of an emerging malware family.

Abstract: A robotic arm capable of picking and placing multi-size wafers includes a first picking and placing unit, a second picking and placing unit and a base. The first picking and placing unit is to transport a first-size or second-size wafer from a first position to a second position. The second picking and placing unit, disposed adjacent to the first picking and placing unit, is to transport the first-size or second-size wafer from the first position to the second position. The base is to construct the first picking and placing unit and the second picking and placing unit. The first picking and placing unit and the second picking and placing unit are identically structured, each of these two units has a frame with adjustable spacing, and thus these two units are able to transport the first-size and second-size wafers simultaneously.

Abstract: A level shifter includes a low-level adjustment circuit, a comparator circuit, and a high-level adjustment circuit. The low-level adjustment circuit pulls down a level of one between a first input node and a second input node to a first low supply voltage. The comparator outputs a one having higher level between the level of the first input node and a second low supply voltage to a first output node, wherein the second low supply voltage is higher than the first low supply voltage. The high-level adjustment circuit selectively adjusts the level of the first output node according to the level of the first input node and the level of the second input node to generate an output signal.

Abstract: A semiconductor memory device includes a substrate; a control gate disposed on the substrate; a source diffusion region disposed in the substrate and on a first side of the control gate; a select gate disposed on the source diffusion region, wherein the select gate has a recessed top surface; a charge storage structure disposed under the control gate; a first spacer disposed between the select gate and the control gate and between the charge storage structure and the select gate; a wordline gate disposed on a second side of the control gate opposite to the select gate; a second spacer between the wordline gate and the control gate; and a drain diffusion region disposed in the substrate and adjacent to the wordline gate.

Abstract: A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.

Abstract: A buffer circuit and a multiplexer using the buffer are provided. The buffer may selectively operate at a first mode or a second mode. The buffer includes a first signal input terminal, a first signal output terminal, and a path circuit coupled between the first signal input terminal and the first signal output terminal. The path circuit has a voltage source terminal. In response to the buffer operating at the first mode, a first signal transmission path is formed in the path circuit and between the first signal input terminal and the first signal output terminal. The first signal transmission path is disconnected from the voltage source terminal.

Abstract: A patch having expansion and supporting effects, comprising a body (10, 10A, 10B), at least one first support member (20, 20A, 20B), and at least one second support member (30, 30A, 0B).

Abstract: A pharmaceutical composition includes a hot-water extract of Codium fragile as an effective ingredient for treating or preventing arthritis, which is a highly effective natural product-derived composition available for cosmetics, beverages, functional foods, etc. which are expected for the alleviation of arthritis.

Abstract: A semiconductor device includes a substrate, having cell region and high-voltage region. A memory cell is on the substrate within the cell region. The memory cell includes a memory gate structure and a selection gate structure on the substrate. A first spacer is sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure. First high-voltage transistor is on the substrate within the high-voltage region. A first composite gate structure of the first high-voltage transistor includes a first gate structure on the substrate, an insulating layer with a predetermined thickness on the substrate in a -like structure or an L-like structure at cross-section, and a second gate structure on the insulating layer along the -like structure or the L-like structure. The selection gate structure and the second gate structure are originated from a same preliminary conductive layer.

Abstract: A semiconductor device includes a substrate, having cell region and high-voltage region. A memory cell is on the substrate within the cell region. The memory cell includes a memory gate structure and a selection gate structure on the substrate. A first spacer is sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure. First high-voltage transistor is on the substrate within the high-voltage region. A first composite gate structure of the first high-voltage transistor includes a first gate structure on the substrate, an insulating layer with a predetermined thickness on the substrate in a -like structure or an L-like structure at cross-section, and a second gate structure on the insulating layer along the -like structure or the L-like structure. The selection gate structure and the second gate structure are originated from a same preliminary conductive layer.

Abstract: A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; forming a second gate structure on the substrate and on one side of the first gate structure; forming a third gate structure on the substrate and on another side of the first gate structure; forming source/drain regions adjacent to the second gate structure and the third gate structure; and forming contact plugs to contact the first gate structure, the second gate structure, the third gate structure, and the source/drain regions.

Abstract: A patch having expansion and supporting effects, comprising a body (10, 10A, 10B), at least one first support member (20, 20A, 20B), and at least one second support member (30, 30A, 0B).

Abstract: An integrated circuit includes a path logic and a timing fixing circuit. The path logic is coupled between an output pin of a first circuit and an input pin of a second circuit. The timing fixing circuit has an input pin coupled to the path logic, and is used to adjust a propagation delay of the path logic. The timing fixing circuit introduces no short-circuit current under normal operation.