Patents by Inventor Chun-Yen Chen

Chun-Yen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11520123
    Abstract: An optical photographing assembly includes, in order from an object side to an image side along an optical axis, a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element has positive refractive power. The third lens element has at least one of an object-side surface and an image-side surface being aspheric. The fourth lens element has at least one of an object-side surface and an image-side surface being aspheric. The fifth lens element has at least one of an object-side surface and an image-side surface being aspheric, wherein at least one of the object-side surface and the image-side surface of the fifth lens element includes at least one inflection point.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: December 6, 2022
    Assignee: LARGAN PRECISION CO., LTD.
    Inventor: Chun-Yen Chen
  • Patent number: 11514718
    Abstract: A human face identification apparatus, a distributed human face identification system and a corresponding method are provided. The method includes obtaining a human face block from an image, identifying a data of a person corresponding to the human face block according to a client database by a client apparatus, controlling the client apparatus to transmit the human face block to a server apparatus and controlling the server apparatus to identify the human face block according to a server database when the data of the person corresponding to the human face block cannot be identified by the client apparatus, and copying the data of the person corresponding to the human face block from the server database to the client database when the data of the person is identified according to the server database by the server apparatus.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: November 29, 2022
    Assignee: QNAP Systems, Inc.
    Inventor: Chun-Yen Chen
  • Patent number: 11513318
    Abstract: An optical photographing lens assembly includes, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof. The second lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The third lens element has two surfaces being both aspheric. The fourth lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof, wherein two surfaces thereof are aspheric. The fifth lens element has an image-side surface being convex in a paraxial region thereof, wherein two surfaces thereof are aspheric.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: November 29, 2022
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Dung-Yi Hsieh, Chun-Yen Chen, Chun-Che Hsueh, Hsin-Hsuan Huang
  • Patent number: 11516513
    Abstract: In one method, the current block is partitioned into multiple final sub-blocks using one or more stages of sub-tree partition comprising ternary tree partition and at least one other-type partition, where ternary partition tree is excluded from the sub-tree partition if a current sub-tree depth associated with a current sub-block is greater than a first threshold and the first threshold is an integer greater than or equal to 1. In another method, if a test condition is satisfied, the current block is encoded or decoded using a current Inter mode selected from a modified group of Inter tools, where the modified group of Inter tools is derived from an initial group of Inter tools by removing one or more first Inter tools from the initial group of Inter tools, replacing one or more second Inter tools with one or more complexity-reduced Inter tools, or both.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: November 29, 2022
    Assignee: MEDIATEK INC.
    Inventors: Chun-Chia Chen, Chia-Ming Tsai, Yu-Chi Su, Chen-Yen Lai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang, Han Huang
  • Publication number: 20220375752
    Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.
    Type: Application
    Filed: August 8, 2022
    Publication date: November 24, 2022
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
  • Patent number: 11508585
    Abstract: A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Liang-Guang Chen, Kei-Wei Chen, Hung Yen, Ting-Hsun Chang, Chi-Hsiang Shen, Li-Chieh Wu, Chi-Jen Liu
  • Patent number: 11507533
    Abstract: A data query method and apparatus are disclosed. The method includes: determining a target directory block including m directory entries and m file names, where the m directory entries one-to-one correspond to the m file names, and the m directory entries and the m file names are sequentially arranged according to a preset rule; determining a current first set and a current second set based on a binary search algorithm and the target directory block; determining a first common prefix between a to-be-accessed file name and a file name in the current second set; comparing the to-be-accessed file name with a third file name character by character from a first character after the first common prefix; and if the to-be-accessed file name is the same as the third file name, obtaining data of a to-be-accessed file based on a directory entry corresponding to the third file name.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: November 22, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xiang Gao, Wei Du, Chun Yen Chen, Ning Wang
  • Patent number: 11508185
    Abstract: A method for collecting facial recognition data includes: locating a first face area from an Nth image frame; extracting a first facial feature defined with S factors; acquiring a second facial feature extracted from a second face area shown in an (N?1)th image frame at a corresponding position; determining whether the first face area is relevant to the second face area, and assigning to the first face area a tracing code; determining whether to store the first facial feature according to a similarity level of the first facial feature to existent data; storing and inputting the first facial feature into a neural network to generate an adjusted feature defined with T factors if the similarity level of the first facial feature to the existent data is not lower than a preset level, wherein T is not smaller than S; acquiring adjusted data generated by inputting the existent data into the neural network; determining whether the person is a registered one according to a similarity level of the adjusted feature to a
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: November 22, 2022
    Assignee: QNAP SYSTEMS, INC.
    Inventors: Chun-Yen Chen, Chan-Cheng Liu, Ting-An Lin
  • Publication number: 20220367398
    Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung CHEN, Yu-Nu HSU, Chun-Chen LIU, Heng-Chi HUANG, Chien-Chen LI, Shih-Yen CHEN, Cheng-Nan HSIEH, Kuo-Chio LIU, Chen-Shien CHEN, Chin-Yu KU, Te-Hsun PANG, Yuan-Feng WU, Sen-Chi CHIANG
  • Publication number: 20220350560
    Abstract: A display control method applicable to an all-in-one (AIO) computer is provided. The AIO computer includes a first monitor and a second monitor. The display control method includes: receiving a control instruction from the first monitor; projecting a display content on the second monitor according to the control instruction; and selectively enabling a touch control function of the second monitor according to the control instruction.
    Type: Application
    Filed: May 2, 2022
    Publication date: November 3, 2022
    Inventors: Yuni LAI, Jen-Chiu CHIANG, Meng-Ru HE, Chung-Shang CHI, Jia-Jung KUO, Hsueh-Chih TANG, Shu-Yun CHEN, Chun-Yen HUANG, Chi-Rong HSU, Yi-Ting CHEN
  • Patent number: 11487091
    Abstract: A photographing lens assembly includes seven lens elements, which are, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof. The second lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The seventh lens element has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof. The image-side surface of the seventh lens element includes at least one convex shape in an off-axis region thereof. The object-side surface and the image-side surface of the seventh lens element are aspheric.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: November 1, 2022
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Chun-Che Hsueh, Chun-Yen Chen, Wei-Yu Chen
  • Patent number: 11489010
    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 1, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
  • Patent number: 11488683
    Abstract: Disclosed is a device for detecting the margin of a circuit operating at an operating speed. The device includes: a signal generating circuit generating an input signal including predetermined data; a first adjustable delay circuit delaying the input signal by a first delay amount and thereby generating a delayed input signal; a circuit under test performing a predetermined operation based on a predetermined operation timing and thereby generating a to-be-tested signal according to the delayed input signal; a second adjustable delay circuit delaying the to-be-tested signal by a second delay amount and thereby generating a delayed to-be-tested signal; a comparison circuit comparing the data included in the delayed to-be-tested signal with the predetermined data based on the predetermined operation timing and thereby generating a comparison result; and a calibration circuit determining whether the circuit under test passes a speed test according to the comparison result.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: November 1, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-Yi Kuo, Ying-Yen Chen
  • Publication number: 20220344153
    Abstract: A method for forming a semiconductor device is provided. The method for forming a semiconductor device is provided. The method includes coating a photoresist film over a target layer; performing a lithography process to pattern the photoresist film into a photoresist layer; performing a directional ion bombardment process to the photoresist layer, such that a carbon atomic concentration in the photoresist layer is increased; and etching the target layer using the photoresist layer as an etch mask.
    Type: Application
    Filed: August 9, 2021
    Publication date: October 27, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Tien SHEN, Chih-Kai YANG, Hsiang-Ming CHANG, Chun-Yen CHANG, Ya-Hui CHANG, Wei-Ting CHIEN, Chia-Cheng CHEN, Liang-Yin CHEN
  • Patent number: 11469203
    Abstract: A method for forming a package structure includes forming an under bump metallization (UBM) layer over a metal pad and forming a photoresist layer over the UBM layer. The method further includes patterning the photoresist layer to form an opening in the photoresist layer. The method also includes forming a first bump structure over the first portion of the UBM layer. The first bump structure includes a first barrier layer over a first pillar layer. The method includes placing a second bump structure over the first bump structure. The second bump structure includes a second barrier layer over a second pillar layer. The method further includes reflowing the first bump structure and the second bump structure to form a solder joint between a first inter intermetallic compound (IMC) and a second IMC.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: October 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
  • Patent number: 11462408
    Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: October 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
  • Publication number: 20220308319
    Abstract: An optical photographing assembly includes, in order from an object side to an image side along an optical axis, a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element has positive refractive power. The third lens element has at least one of an object-side surface and an image-side surface being aspheric. The fourth lens element has at least one of an object-side surface and an image-side surface being aspheric. The fifth lens element has at least one of an object-side surface and an image-side surface being aspheric, wherein at least one of the object-side surface and the image-side surface of the fifth lens element includes at least one inflection point.
    Type: Application
    Filed: June 8, 2022
    Publication date: September 29, 2022
    Inventor: Chun-Yen CHEN
  • Publication number: 20220302833
    Abstract: A boost converter includes an inductor and a diode electrically connected in series between an input voltage and an output voltage; a transistor electrically coupled to an interconnected node of the inductor and the diode; and a controller that controls switching of the transistor according to a transient mode and an estimated load current. The output voltage in a light-to-heavy load transient mode has at least one first valley point with a value of a transient voltage threshold, followed by at least one second valley point with a value higher than the first valley point, before exiting the light-to-heavy load transient mode.
    Type: Application
    Filed: March 17, 2021
    Publication date: September 22, 2022
    Inventors: Chun-Yen Chen, Chien-Hung Tsai, Chia-Hsuan Huang, Teng-Kuei Wu
  • Patent number: 11449927
    Abstract: Device and method for implementing a vehicle sharing reward program. The present invention provides for a cost-sharing plan where two or more constituencies share the rental cost associated with a user who rents a shared vehicle in a vehicle sharing program. This results in a reimbursement of the rental cost to the user. When enrolling in the vehicle sharing reward program, the user is given a health prescription to adhere to on any trip taken while using a shared vehicle. On a selected travel route, the user visits a vehicle sharing station, where the sharing station includes a kiosk that the user uses to check-in and upload relevant information such as distance traveled and locations visited. By complying with the health prescription issued to the user, the user can have its total rental cost reimbursed.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: September 20, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chun-Yen Chen, Jian-Ren Chen, Su-Chen Huang, June-Ray Lin
  • Patent number: 11451222
    Abstract: A reliability detection device includes a control circuit, oscillator circuits, and an output circuit. The control circuit is configured to generate enable signals according to a mode signal. The oscillator circuits output oscillating signals, in which each of the oscillator circuits is configured to generate a corresponding oscillating signal in the oscillating signals according to a switching signal when the mode signal has a first logic value, and generate the corresponding oscillating signal according to a corresponding enable signal in the enable signals when the mode signal has a second logic value, and the switching signal is associated with a functional circuit. The output circuit is configured to output a detection signal according to the oscillating signals when the mode signal has the second logic value, in which the detection signal is to indicate a reliability of the functional circuit.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: September 20, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Wen-Hsuan Hsu, Chun-Yi Kuo, Ying-Yen Chen