Patents by Inventor Chung Foong Tan
Chung Foong Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110044115Abstract: A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices.Type: ApplicationFiled: August 21, 2009Publication date: February 24, 2011Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Elgin Quek, Chunshan Yin, Shyue Seng Tan, Jae Gon Lee, Chung Foong Tan
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Publication number: 20100315884Abstract: A non-volatile memory device (and method of manufacture) is disclosed and structured to enable a write operation using an ionization impact process in a first portion of the device and a read operation using a tunneling process in a second portion of the device. The non-volatile memory device (1) increases hot carrier injection efficiency, (2) decreases power consumption, and (3) enables voltage and device scaling in the non-volatile memory devices.Type: ApplicationFiled: June 16, 2009Publication date: December 16, 2010Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Eng Huat Toh, Chung Foong Tan, Shyue Seng Tan, Jae Gon Lee, Elgin Quek
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Patent number: 7846800Abstract: A circuit having a circuit control terminal, a primary circuit and a protection circuit is provided. The primary circuit includes a primary control terminal and a primary gate oxide of a thickness T1. The primary control terminal is coupled to the circuit control terminal. The protection circuit having a protection control terminal is coupled to the primary circuit. The protection circuit includes a protection gate oxide of a second thickness T2 which is less than T1. The protection gate oxide reduces plasma induced damage in the primary circuit.Type: GrantFiled: March 6, 2008Date of Patent: December 7, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Chung Foong Tan, Jae Gon Lee, Lee Wee Teo, Elgin Quek, Chunshan Yin
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Publication number: 20100304556Abstract: A method of manufacture of an integrated circuit system includes: providing a mesa over a substrate; forming a trench in the substrate adjacent the mesa; forming a second gate and a charge storage material along a trench sidewall; and forming a first gate from the mesa.Type: ApplicationFiled: May 26, 2009Publication date: December 2, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Chunshan Yin, Jae Gon Lee, Shyue Seng Tan, Elgin Kiok Boone Quek, Chung Foong Tan, Lee Wee Teo
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Patent number: 7833888Abstract: An integrated circuit system that includes: providing a substrate including an active device with a gate top surface exposed; implanting a do pant within the gate to alter the grain size of the gate material; forming a dielectric layer over the active device and the substrate; and annealing the integrated circuit system to transfer the stress of the dielectric layer into the active device.Type: GrantFiled: May 6, 2008Date of Patent: November 16, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chung Foong Tan, Jae Gon Lee, Lee Wee Teo, Elgin Kiok Boone Quek
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Patent number: 7816274Abstract: The electrical performance enhancing effects of inducing strain in semiconductor devices is made substantially uniform across a substrate having a varying population density of device components by selectively spacing apart the strain-inducing structures from the effected regions of the semiconductor devices depending upon the population density of device components. Differing separation distances are obtained by selectively forming sidewall spacers on device components, such as MOS transistor gate electrodes, in which the sidewall spacers have a relatively small width in regions having a relatively high density of device components, and a relatively larger width in regions having a relatively low density of device components. By varying the separation distance of strain-inducing structures from the effected components, uniform electrical performance is obtained in the various components of the devices in an integrated circuit regardless of the component population density.Type: GrantFiled: March 27, 2008Date of Patent: October 19, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Lee Wee Teo, Chung Foong Tan, Alain Chan, Elgin Kiok Boone Quek
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Publication number: 20100258868Abstract: A method of manufacture of an integrated circuit system includes: providing a second layer between a first layer and a third layer; forming an active device over the third layer; forming the third layer to form an island region underneath the active device; forming the second layer to form a floating second layer with an undercut beneath the island region; and depositing a fourth layer around the island region and the floating second layer.Type: ApplicationFiled: April 13, 2009Publication date: October 14, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Chunshan Yin, Lee Wee Teo, Chung Foong Tan, Jae Gon Lee
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Publication number: 20090280629Abstract: An integrated circuit system that includes: providing a substrate including an active device with a gate top surface exposed; implanting a dopant within the gate to alter the grain size of the gate material; forming a dielectric layer over the active device and the substrate; and annealing the integrated circuit system to transfer the stress of the dielectric layer into the active device.Type: ApplicationFiled: May 6, 2008Publication date: November 12, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Chung Foong Tan, Jae Gon Lee, Lee Wee Teo, Elgin Kiok Boone Quek
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Publication number: 20090246920Abstract: The electrical performance enhancing effects of inducing strain in semiconductor devices is made substantially uniform across a substrate having a varying population density of device components by selectively spacing apart the strain-inducing structures from the effected regions of the semiconductor devices depending upon the population density of device components. Differing separation distances are obtained by selectively forming sidewall spacers on device components, such as MOS transistor gate electrodes, in which the sidewall spacers have a relatively small width in regions having a relatively high density of device components, and a relatively larger width in regions having a relatively low density of device components. By varying the separation distance of strain-inducing structures from the effected components, uniform electrical performance is obtained in the various components of the devices in an integrated circuit regardless of the component population density.Type: ApplicationFiled: March 27, 2008Publication date: October 1, 2009Inventors: Lee Wee Teo, Chung Foong Tan, Alain Chan, Elgin Kiok Boone Quek
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Publication number: 20090224326Abstract: A circuit having a circuit control terminal, a primary circuit and a protection circuit is provided. The primary circuit includes a primary control terminal and a primary gate oxide of a thickness T1. The primary control terminal is coupled to the circuit control terminal. The protection circuit having a protection control terminal is coupled to the primary circuit. The protection circuit includes a protection gate oxide of a second thickness T2 which is less than T1. The protection gate oxide reduces plasma induced damage in the primary circuit.Type: ApplicationFiled: March 6, 2008Publication date: September 10, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Chung Foong TAN, Jae Gon LEE, Lee Wee TEO, Elgin QUEK, Chunshan YIN
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Publication number: 20090221117Abstract: An integrated circuit system that includes: providing a substrate including a first region and a second region; forming a first device over the first region and a resistance device over the second region; forming a first dielectric layer and a second dielectric layer over the substrate; removing a portion of the second dielectric layer; and annealing the integrated circuit system to remove dopant from the resistance device.Type: ApplicationFiled: February 29, 2008Publication date: September 3, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Shyue Seng Tan, Lee Wee Teo, Chung Foong Tan, Jae Gon Lee, Elgin Kiok Boone Quek
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Publication number: 20090184341Abstract: A method (and semiconductor device) of fabricating a semiconductor device eliminates shallow trench isolation (STI) recess in embedded SiGe p-type field effect transistor (pFET) structures. This increases device performance by improving isolation and decreasing leakage current caused by SiGe facet growth and silicide encroachment at the STI. A mask is selectively formed over the STI and adjacent nFET regions to protect them during formation (e.g., reactive ion etching (RIE)) of the embedded source/drain (S/D) regions of the pFET. The mask also extends over the STI edge by a predetermined distance to cover a portion of the embedded S/D region disposed between the STI and gate structure. This helps protect or isolate the STI region during SiGe layer formation in the defined embedded S/D regions.Type: ApplicationFiled: January 17, 2008Publication date: July 23, 2009Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Yung Fu Chong, Lee Wee Teo, Shyue Seng Tan, Chung Foong Tan
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Publication number: 20090179226Abstract: Methods (and semiconductor substrates produced therefrom) of fabricating (n?1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n?1 SDOI substrates.Type: ApplicationFiled: January 15, 2008Publication date: July 16, 2009Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Lee Wee Teo, Chung Foong Tan, Shyue Seng Tan, Elgin Quek
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Publication number: 20090170268Abstract: A process for fabricating a semiconductor device, such as a strained-channel transistor, includes forming epitaxial regions in a substrate in proximity to a gate electrode in which the surface profile of the epitaxial regions is defined by masking sidewall spacers adjacent the gate electrode. The epitaxial regions are formed by depositing an epitaxial material into cavities selectively etched into the semiconductor substrate on either side of the gate electrode. The masking sidewall spacers limit the thickness of the epitaxial deposited material in proximity of the gate electrode, such that the upper surface of the epitaxial material is substantially the same as the principal surface of the semiconductor substrate. Doped regions are formed in the channel region beneath the gate electrode using an angled ion beam, such that doping profiles of the implanted regions are substantially unaffected by surface irregularities in the epitaxially-deposited material.Type: ApplicationFiled: December 27, 2007Publication date: July 2, 2009Inventors: Lee Wee Teo, Alain Chan, Chung Foong Tan, Elgin Kiok Boone Quek
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Patent number: 7400018Abstract: A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode.Type: GrantFiled: August 7, 2006Date of Patent: July 15, 2008Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chung Foong Tan, Jinping Liu, Hyeok Jae Lee, Bangun Indajang, Eng Fong Chor, Shiang Yang Ong
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Patent number: 7169675Abstract: A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.Type: GrantFiled: July 7, 2004Date of Patent: January 30, 2007Assignee: Chartered Semiconductor Manufacturing, LtdInventors: Chung Foong Tan, Jinping Liu, Hyeokjae Lee, Kheng Chok Tee, Elgin Quek
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Publication number: 20060270168Abstract: A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode.Type: ApplicationFiled: August 7, 2006Publication date: November 30, 2006Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Chung Foong Tan, Jinping Liu, Hyeok Lee, Bangun Indajang, Eng Fong Chor, Shiang Yang Ong
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Patent number: 7109099Abstract: A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode.Type: GrantFiled: October 17, 2003Date of Patent: September 19, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chung Foong Tan, Jinping Liu, Hyeok Jae Lee, Bangun Indajang, Eng Fong Chor, Shiang Yang Ong
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Patent number: 7071069Abstract: A pocket implant process to reduce defects. We provide a gate structure, on a semiconductor substrate doped with a first conductivity type dopant. We perform a pocket amorphizing implantation procedure to form a pocket implant region adjacent to the gate structure, and an amorphous pocket region. Next, we perform a shallow amorphizing implant to form an amorphous shallow implant region. The amorphous shallow implant region being formed at a second depth above the amorphous pocket region. The substrate above the amorphous shallow implant region preferably remains crystalline. We perform a S/D implant procedure to form Deep S/D regions. We perform an anneal procedure preferably comprised of a first soak step and a second spike step to recrystalilze the amorphous shallow implant region and the amorphous pocket region, The defects created by the pocket implant are reduced by the shallow amorphous implant.Type: GrantFiled: December 22, 2003Date of Patent: July 4, 2006Assignee: Chartered Semiconductor Manufacturing, LTDInventors: Chung Foong Tan, Hyeokjae Lee, Eng Fong Chor, Elgin Quek