Patents by Inventor Chung-Hao Chen

Chung-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11964528
    Abstract: System and method for improving braking efficiency by increasing the magnitude of a frictional force between a tire of a vehicle wheel and a road surface. Braking efficiency may be improved by controlling the normal force applied on the wheel, with an active suspension actuator, based on the wheel's slip ratio.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: April 23, 2024
    Assignee: ClearMotion, Inc.
    Inventors: Aditya Chandrashekhar Chetty, Allen Chung-Hao Chen
  • Patent number: 11967570
    Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: April 23, 2024
    Assignee: MediaTek Inc.
    Inventors: Chia-Hao Hsu, Tai-Yu Chen, Shiann-Tsong Tsai, Hsing-Chih Liu, Yao-Pang Hsu, Chi-Yuan Chen, Chung-Fa Lee
  • Patent number: 11959623
    Abstract: The present disclosure provides a connecting device and a lamp system. The connecting device is used to connect multiple lamps to form the lamp system. The connecting device includes a connecting element, a cover, and a shell. The cover is mounted on the connecting element and includes at least two first assembling members. The shell is detachably mounted on the cover. The shell includes a side wall, an opening, multiple gateways, and at least two second assembling members. The side wall surrounds a space. The opening and the gateways all are formed on a top of the side wall and communicate with the space. A portion of each of the lamps is received in one of the gateways. The second assembling members are disposed on the side wall and face each other in a radial line of the shell, and respectively engage with the first assembling members.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: April 16, 2024
    Assignee: Radiant Opto-Electronics Corporation
    Inventors: Chih-Hung Ju, Cheng-Ang Chang, Guo-Hao Huang, Chung-Kuang Chen
  • Publication number: 20240111139
    Abstract: An imaging lens assembly module includes a lens barrel, a catadioptric lens assembly, an imaging lens assembly, a first fixing element and a second fixing element. The lens barrel has a first relying surface and a second relying surface, which face towards an object side of the imaging lens assembly module. The catadioptric lens assembly relies on the first relying surface. The imaging lens assembly is disposed on an image side of the catadioptric lens assembly, and relies on the second relying surface. The first fixing element is for fixing the catadioptric lens assembly to the lens barrel. The second fixing element is for fixing the imaging lens assembly to the lens barrel. The catadioptric lens assembly is for processing at least twice internal reflections of an image light in the imaging lens assembly module, and for providing optical refractive power.
    Type: Application
    Filed: September 26, 2023
    Publication date: April 4, 2024
    Inventors: Lin-An CHANG, Chung Hao CHEN, Wen-Yu TSAI, Ming-Ta CHOU
  • Publication number: 20240088033
    Abstract: A method of forming a semiconductor device is provided. A transistor is formed at a first side of the substrate and a first dielectric layer is formed aside the transistor. A first metal via is formed through the first dielectric layer and aside the transistor. A first interconnect structure is formed over the first side of the substrate and electrically connected to the transistor and the first metal via. The substrate is thinned from a second side of the substrate. A capacitor is formed at the second side of the substrate and a second dielectric layer is formed aside the capacitor. A second metal via is formed through the second dielectric layer and the substrate and electrically connected to the first metal via.
    Type: Application
    Filed: March 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Kai Chan, Chung-Hao Tsai, Chuei-Tang WANG, Wei-Ting Chen
  • Publication number: 20240088078
    Abstract: Packaged memory devices including memory devices hybrid bonded to logic devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first memory die including a first memory cell electrically coupled to a first word line; a second memory cell electrically coupled to the first word line; and a first interconnect structure electrically coupled to the first word line; a circuitry die including a second interconnect structure, a first conductive feature of the first interconnect structure being bonded to a second conductive feature of the second interconnect structure through metal-to-metal bonds; and a word line driver electrically coupled to the first word line between the first memory cell and the second memory cell, the word line driver being electrically coupled to the first word line through the first interconnect structure and the second interconnect structure.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 14, 2024
    Inventors: Chung-Hao Tsai, Yih Wang, Wei-Ting Chen, Chuei-Tang Wang, Chen-Hua Yu
  • Publication number: 20240076422
    Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 7, 2024
    Inventors: Jing-Cherng TSAI, Jen-Long WU, Wen-Hao KANG, Kuei-Pin LIN, Jing-Yu LEE, Jun-Ye HONG, Zih-Yu SHIH, Cheng-Hung CHIANG, Gang-Wei SHEN, Yu-Chuan SUNG, Chung-Hua WENG, Hsing-Ya CHEN
  • Patent number: 11923396
    Abstract: An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wei Hsu, Tsai-Hao Hung, Chung-Yu Lin, Ying-Hsun Chen
  • Patent number: 11923647
    Abstract: A conductive mechanism includes two bases, an inner conductive spring and an outer conductive spring. The two bases are opposite to each other. Each of the bases includes a surface and a partition wall protruding relative to the surface. The inner conductive spring is disposed at inner sides of the two partition walls of the two bases. The outer conductive spring is disposed at outer sides of the two partition walls of the two bases. At least one of two ends of each of the inner conductive spring and the outer conductive spring rotatably abuts against the surface of one of the bases.
    Type: Grant
    Filed: February 3, 2023
    Date of Patent: March 5, 2024
    Assignee: Radiant Opto-Electronics Corporation
    Inventors: Chung-Kuang Chen, Chih-Hung Ju, Guo-Hao Huang
  • Publication number: 20240071535
    Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.
    Type: Application
    Filed: October 16, 2022
    Publication date: February 29, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Chung-Hao Chen, Chi-Hsiu Hsu, Chi-Fa Lien, Ying-Ting Lin, Cheng-Hsiao Lai, Ya-Nan Mou
  • Publication number: 20240068652
    Abstract: The present disclosure provides a connecting device and a lamp system. The connecting device is used to connect multiple lamps to form the lamp system. The connecting device includes a connecting element, a cover, and a shell. The cover is mounted on the connecting element and includes at least two first assembling members. The shell is detachably mounted on the cover. The shell includes a side wall, an opening, multiple gateways, and at least two second assembling members. The side wall surrounds a space. The opening and the gateways all are formed on a top of the side wall and communicate with the space. A portion of each of the lamps is received in one of the gateways. The second assembling members are disposed on the side wall and face each other in a radial line of the shell, and respectively engage with the first assembling members.
    Type: Application
    Filed: April 27, 2023
    Publication date: February 29, 2024
    Inventors: Chih-Hung JU, Cheng-Ang CHANG, Guo-Hao HUANG, Chung-Kuang CHEN
  • Patent number: 11916146
    Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
  • Publication number: 20240001924
    Abstract: A vehicle control system for a vehicle is provided. The vehicle control system may be configured to adjust a normal component of a wheel force at one or more wheels of the vehicle and steer one or more rear wheels of the vehicle to improve vehicle dynamics during a road event (e.g., braking event, steering event). The vehicle control system may generate cues to a user to provide an appropriate input based on reference road information, forward-looking road information, and/or vehicle sensor data.
    Type: Application
    Filed: November 22, 2021
    Publication date: January 4, 2024
    Applicant: ClearMotion, Inc.
    Inventors: Marco Giovanardi, Allen Chung-Hao Chen
  • Patent number: 11806710
    Abstract: A semiconductor package structure includes a substrate, a die and a conductive structure. The die is disposed on or within the substrate. The die has a first surface facing away from the substrate and includes a sensing region and a pad at the first surface of the die. The first surface of the die has a first edge and a second edge opposite to the first edge. The sensing region is disposed adjacent to the first edge. The pad is disposed away from the first edge. The conductive structure electrically connects the pad and the substrate. The sensing region has a first end distal to the first edge of the first surface of the die. A distance from the first end of the sensing region to a center of the pad is equal to or greater than a distance from the first end of the sensing region to the first edge of the first surface of the die.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: November 7, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsiao-Yen Lee, Ying-Te Ou, Chin-Cheng Kuo, Chung Hao Chen
  • Patent number: 11784110
    Abstract: A semiconductor package may include a substrate; a microelectromechanical device disposed on the substrate; an interconnection structure connecting the substrate to the microelectromechanical device; and a metallic sealing structure surrounding the interconnection structure.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: October 10, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chung Hao Chen, Chin-Cheng Kuo
  • Publication number: 20230271594
    Abstract: A vehicle control system for a vehicle having a braking system and active suspension system is provided. The vehicle control system may be configured to adjust a normal component of a wheel force at one or more wheels of the vehicle to increase an average traction force at the one or more wheels during a braking event. The vehicle control system may adjust a normal component of a wheel force at one or more wheels based on reference road information, forward-looking road information, and/or vehicle sensor data.
    Type: Application
    Filed: July 9, 2021
    Publication date: August 31, 2023
    Applicant: ClearMotion, Inc.
    Inventor: Allen Chung-Hao Chen
  • Publication number: 20230017774
    Abstract: Methods are provided for proactively controlling a component of a system. The system may comprise a vehicle and the component may comprise a suspension of the vehicle. According to various aspects, methods may include obtaining information regarding a travel surface along a travel path that the system will travel at a future time and, based on the information regarding the travel surface, controlling the component of the system to traverse the travel surface. Controlling the component based on the information regarding the travel surface may comprise comparing the information regarding the travel surface to information regarding at least one physical constraint of the system and/or comparing frequency content of the information regarding the travel surface to a threshold frequency. Proactive control methods may provide improved response to disturbances and improved tracking and isolation because a suspension may be controlled with reduced or substantially zero delay.
    Type: Application
    Filed: December 30, 2020
    Publication date: January 19, 2023
    Applicant: ClearMotion, Inc.
    Inventors: Marco Giovanardi, William Graves, Allen Chung-Hao Chen
  • Publication number: 20220379679
    Abstract: In some embodiments, methods and systems may be used to control operation of various systems of the vehicle based on road features included in an upcoming portion of a road surface located along a path of travel of the vehicle. This control may either be based on a probability of encountering a road feature on the road surface 5 and/or frequency information related to the upcoming portion of the road surface.
    Type: Application
    Filed: November 3, 2020
    Publication date: December 1, 2022
    Applicant: ClearMotion, Inc.
    Inventors: John Parker Eisenmann, William Graves, Allen Chung-Hao Chen, Marco Giovanardi
  • Publication number: 20220281456
    Abstract: Systems and methods described herein include implementation of road surface-based localization techniques for advanced vehicle features and control methods including advanced driver assistance systems (ADAS), lane drift detection, passing guidance, bandwidth conservation and caching based on road data, vehicle speed correction, suspension and vehicle system performance tracking and control, road estimation calibration, and others.
    Type: Application
    Filed: December 23, 2021
    Publication date: September 8, 2022
    Applicant: ClearMotion, Inc.
    Inventors: Marco Giovanardi, Hou-Yi Lin, Stefan Schulze, John Parker Eisenmann, William Graves, Marcus Joseph Proctor, Nikolaos Karavas, Allen Chung-Hao Chen, Jack A. Ekchian
  • Patent number: 11417412
    Abstract: A cell trace circuit includes a memory cell, a voltage generator and a measuring circuit. The memory cell has a resistor and a memory layer coupled in series to have a top electrode, a middle electrode and a bottom electrode, wherein the resistor and the memory layer are coupled at the middle electrode. The voltage generator provides a test bias to the memory cell ranging from a negative voltage to a positive voltage in a reset path or ranging from the positive voltage to the negative voltage in a set path. The measuring circuit is to determine a current (I) and a voltage (V) crossing the memory layer by the test bias.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: August 16, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Hao Chen, Hsiao-Hua Lu