Patents by Inventor Chung-Hsun Lee

Chung-Hsun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10380024
    Abstract: The present disclosure provides a dynamic random access memory (DRAM), and a method of operating the same. The DRAM includes a memory row and a buffer. The memory row is configured to store a data, wherein the memory row does not provide the data to the buffer in response to a request to read the data. The buffer is configured to store the data as a temporarily-stored data, wherein the buffer provides the temporarily-stored data in response to the request.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: August 13, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10354713
    Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 16, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10338831
    Abstract: Present disclosure includes a system for preserving data in a volatile memory and a method thereof. The volatile memory comprises a plurality of refreshing units, and each of the refreshing units comprises a plurality of word lines for storing data. The system comprises an accessing unit. The accessing unit is configured to detect a row-hammer indication indicating a first word line is frequently accessed, wherein the accessing unit is configured to copy data stored in the first word line to a second word line when the row-hammer indication is detected on the first word line, wherein the data stored in the first and the second word lines are available to be selectively accessed.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: July 2, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Publication number: 20190196726
    Abstract: The present disclosure provides a dynamic random-access memory (DRAM) with a data correction function and a method of operating the same. The DRAM includes a memory array; a control circuit configured to receive an inputting data and a temperature signal; a first error-correction code (ECC1) circuit configured to generate a first encoded data from the inputting data; and a second error-correction code (ECC2) circuit configured to generate a second encoded data from the inputting data.
    Type: Application
    Filed: March 12, 2018
    Publication date: June 27, 2019
    Inventors: CHUNG-HSUN LEE, Hsien-Wen Liu
  • Publication number: 20190196733
    Abstract: The present disclosure provides a hybrid memory system and a method of operating the same. The hybrid memory system includes a non-volatile memory, a volatile memory and a controller. The volatile memory stores data. The controller is configured to move the data from the volatile memory to the non-volatile memory in response to a command to enter a power-saving mode. The controller precludes the volatile memory from having a self-refresh operation performed thereon after the movement of the data.
    Type: Application
    Filed: February 20, 2018
    Publication date: June 27, 2019
    Inventors: CHUNG-HSUN LEE, HSIEN-WEN LIU
  • Publication number: 20190196902
    Abstract: The present disclosure provides a dynamic random-access memory (DRAM) with a data correction function and a method of operating the same. The DRAM includes a memory array; a control circuit configured to receive a reading address and a defect information of the reading address; an access circuit configured to generate a reading data from the memory array according to the reading address from the control circuit; and a modifying circuit connected to the access circuit and the control circuit, wherein the modifying circuit is configured to modify a part of the reading data according to the defect information.
    Type: Application
    Filed: February 26, 2018
    Publication date: June 27, 2019
    Inventors: CHUNG-HSUN LEE, HSIEN-WEN LIU
  • Patent number: 10332579
    Abstract: The present disclosure provides a dynamic random access memory (DRAM) including a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data. The second cell is configured to have a stored electrical energy by being programmed with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a refresh rate of the refresh unit to a first refresh rate when the stored electrical energy of the second cell becomes lower than a threshold electrical energy, wherein the threshold electrical energy is higher than a standard electrical energy for determining binary logic.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: June 25, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10332580
    Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: June 25, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Publication number: 20190171572
    Abstract: The present disclosure provides a dynamic random access memory (DRAM), and a method of operating the same. The DRAM includes a memory row and a buffer. The memory row is configured to store a data, wherein the memory row does not provide the data to the buffer in response to a request to read the data. The buffer is configured to store the data as a temporarily-stored data, wherein the buffer provides the temporarily-stored data in response to the request.
    Type: Application
    Filed: January 2, 2018
    Publication date: June 6, 2019
    Inventors: CHUNG-HSUN LEE, HSIEN-WEN LIU
  • Publication number: 20190164589
    Abstract: The present disclosure provides a dynamic random access memory (DRAM) including a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data. The second cell is configured to have a stored electrical energy by being programmed with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a refresh rate of the refresh unit to a first refresh rate when the stored electrical energy of the second cell becomes lower than a threshold electrical energy, wherein the threshold electrical energy is higher than a standard electrical energy for determining binary logic.
    Type: Application
    Filed: February 20, 2018
    Publication date: May 30, 2019
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10297304
    Abstract: An operating method of a memory device includes the following operations: during a refresh operation with the first refresh rate, generating a first ECC according to first data, and generating a second ECC according to second data; determining whether an error exists in the first data or not during the refresh operation with a second refresh rate; determining whether the error exists in the second data or not during the refresh operation with a third refresh rate; and if it is determined that the error exists in the first data and/or the second data, correcting the first data and/or the second data. The second refresh rate and the third refresh rate are lower than the first refresh rate, and the third refresh rate is lower than the second refresh rate. The correcting ability of the second ECC is higher than the correcting ability of the first ECC.
    Type: Grant
    Filed: November 12, 2017
    Date of Patent: May 21, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Publication number: 20190147936
    Abstract: An operating method of a memory device includes the following operations: during a refresh operation with the first refresh rate, generating a first ECC according to first data, and generating a second ECC according to second data; determining whether an error exists in the first data or not during the refresh operation with a second refresh rate; determining whether the error exists in the second data or not during the refresh operation with a third refresh rate; and if it is determined that the error exists in the first data and/or the second data, correcting the first data and/or the second data. The second refresh rate and the third refresh rate are lower than the first refresh rate, and the third refresh rate is lower than the second refresh rate. The correcting ability of the second ECC is higher than the correcting ability of the first ECC.
    Type: Application
    Filed: November 12, 2017
    Publication date: May 16, 2019
    Inventors: Chung-Hsun LEE, Hsien-Wen LIU
  • Patent number: 10276228
    Abstract: A dynamic random access memory (DRAM) DRAM includes a memory array, a temperature sensor and a control device. The temperature sensor is configured to sense a temperature of the DRAM. The control device is configured to adjust a sense frequency based on a retention ability of the memory array, and to activate the temperature sensor according to the adjusted sense frequency.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: April 30, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Publication number: 20190122747
    Abstract: A memory device includes a memory array, an error correction code (ECC) circuit, and a control circuit. The memory array includes plural memory rows and stores a plurality of data. The control circuit is configured to enter the memory device into a power saving mode with a first refresh rate to refresh the memory array, to control the ECC circuit to generate a first ECC according to first data during refreshing the memory array by the first refresh rate, to reduce the first refresh rate to a second refresh rate, to control the ECC circuit to determine whether an error exists in the first data during refreshing the memory array by the second refresh rate. If the error exists in the first data, the control circuit is further configured to control the ECC circuit to correct the first data.
    Type: Application
    Filed: October 22, 2017
    Publication date: April 25, 2019
    Inventors: Chung-Hsun LEE, Hsien-Wen LIU
  • Patent number: 10269445
    Abstract: A memory device includes a memory array, an error correction code (ECC) circuit, and a control circuit. The memory array includes plural memory rows and stores a plurality of data. The control circuit is configured to enter the memory device into a power saving mode with a first refresh rate to refresh the memory array, to control the ECC circuit to generate a first ECC according to first data during refreshing the memory array by the first refresh rate, to reduce the first refresh rate to a second refresh rate, to control the ECC circuit to determine whether an error exists in the first data during refreshing the memory array by the second refresh rate. If the error exists in the first data, the control circuit is further configured to control the ECC circuit to correct the first data.
    Type: Grant
    Filed: October 22, 2017
    Date of Patent: April 23, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Publication number: 20190115067
    Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.
    Type: Application
    Filed: October 12, 2017
    Publication date: April 18, 2019
    Inventors: Chung-Hsun LEE, Hsien-Wen LIU
  • Publication number: 20190115068
    Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.
    Type: Application
    Filed: November 27, 2018
    Publication date: April 18, 2019
    Inventors: Chung-Hsun LEE, Hsien-Wen LIU
  • Patent number: 10262719
    Abstract: The present disclosure provides a dynamic random access memory (DRAM) and a method of operating the same. The DRAM includes a memory array, a refresh device and an access device. The refresh device is configured to perform a self-refresh operation on the memory array, wherein the self-refresh operation is interrupted in response to an access command. The access device is configured to access the memory array in response to the access command and the interruption of the self-refresh operation.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 16, 2019
    Assignee: Nanya Technology Corporation
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10236035
    Abstract: The present disclosure provides a dynamic random access memory (DRAM). The DRAM includes a refresh unit, an accessing device and a refresh device. The refresh unit has a plurality of memory rows. The accessing device is configured to access the memory rows. The refresh device is configured to refresh the refresh unit in a first manner in response to a first event, in which a quantity of accessed memory rows of the refresh unit is not greater than a threshold quantity. The refresh device is configured to refresh the refresh unit in a second manner in response to a second event, in which the quantity of accessed memory rows of the refresh unit is greater than the threshold quantity.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: March 19, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Publication number: 20190066760
    Abstract: The present disclosure provides a DRAM. The DRAM includes a memory array and a control device. The memory array has a plurality of word lines configured to control memory cells. The control device is configured to operate at least one word line of the word lines, derive an information on the operating of the at least word line, and cease maintaining data stored in the memory cells controlled by the at least one word line when the information satisfies a condition.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 28, 2019
    Inventors: Chung-Hsun LEE, Hsien-Wen LIU