Abstract: Disclosed is a scan test data compression method and decoding apparatus for multiple-scan-chain designs. The apparatus comprises a on-chip decoder connected to a tester. The decoder includes a decoding buffer configured as a multilayer architecture, a controller, and a switching box for receiving a shift signal or a copy signal. The decoding buffer is used to store decoded test data. While the decoder decodes the encoded data, it transmits control signals to both the decoding buffer and the switching box from the controller, and sends the decoded data to scan chains of a CUT for testing through the decoding buffer. This invention has the advantages of simple encoding method, high compression rate, low power consumption in testing, and without the fault coverage loss.

Abstract: With the growing practice of doping gates for MOSFETs with boron, problems have been encountered due to later diffusion of the boron into the active region. To block this, argon ions are implanted into the gate pedestal material prior to doping it with boron. The damage caused by the argon ions results in traps that getter the boron atoms, behaving in effect as a diffusion barrier. The invention is directed specifically to gate pedestals that are less than about 3000 Angstroms thick. Under these conditions it has been determined that the implantation energies of the argon ions should not exceed 80 keV. It is also important that the dosage of argon be in the range from 1.times.10.sup.15 to 1.times.10.sup.16 per cm.sup.2. Preferably doses in excess of 5.times.10.sup.15 should be used as they also lead to improvements in subthreshold swing and hot carrier immunity.

Abstract: A sequence generator for generating multiple-pattern sequences utilizing an inverting non-linear autonomous machine is disclosed. The generation of the sequence is based on the interdependency relationship between the bits of the deterministic patterns in the sequences to be generated. The autonomous machine comprises a number of flip-flop cascades each containing a number of flip-flops. The flip-flops in each of the cascades are connected in a way that the output of one flip-flop is connected to the input of the next flip-flop in each cascade. The autonomous machine further comprises a number of XOR gates each feeding its output to the input of a corresponding one of the cascades of flip-flops. The autonomous machine further comprises a switch device that includes a number of switches for receiving the output of each of the flip-flops in the cascades as feedbacks for outputting to the inputs of the XOR gates.

Abstract: A method for suppressing boron penetration in a PMOS with a nitridized polysilicon gate includes steps of 1) growing a layer of gate oxide on a substrate, 2) forming at least one first polysilicon layer on the gate oxide layer, 3) nitridizing the first polysilicon layer, 4) forming a second polysilicon layer on the first polysilicon layer; and 5) implanting B-containing ions into the first and second polysilicon layers for constructing a PMOS structure wherein the nitridizing step suppresses a boron ion from penetration into the substrate. The present invention is characterized in nitridation on a polysilicon gate instead of a gate oxide which can effectively suppress boron penetration, avoid drawbacks resulting from nitridizing a gate oxide, and moreover, improve the reliability of the device owing to the slight nitridation effect in the polysilicon gate and the gate oxide.

Abstract: Disclosed is a thin textured tunnel oxide prepared by thermal oxidation of a thin polysilicon film on Si substrate. Due to the rapid diffusion of oxygen through grain boundries of the thin polysilicon film into the Si substrate and the enhanced oxidation rate at grain boundries, a textured Si/SiO.sub.2 interface is obtained. The textured Si/SiO.sub.2 interface results in localized high fields and causes a much higher electron injection rate. EEPROM memory cells having the textured Si/SiO.sub.2 exhibit a lower electron trapping rate and a lower interface state generation rate even under high field operation.

Abstract: A process is used to fabricate diodes having an emitter contacted p-n junction. A stack of n.sup.+ -type polysilicon layers are formed one upon the other upon a p-type silicon substrate. In an accordingly fabricated diode, native oxide layers that forms between the n.sup.+ -type polysilicon layer and the p-type substrate would be liable to be broken up, and thicker epitaxial layer would be formed between the same. The p-n junction is with a thickness of 0.05-0.2 .mu.m. As the diode is reverse-biased, for example at -5V, leakage current could be less than 1 n.ANG./cm.sup.2. The reverse-bias breakdown voltage could be larger than -100 V. When forward-biased, the ideality factor of the diode is close to unity.