Patents by Inventor Chung-Lung K. Shum
Chung-Lung K. Shum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10474576Abstract: Enabling a prefetch request to be controlled in response to conditions in a receiver of the prefetch request and to conditions in a source of the prefetch request. One or more processors identify, based on a prefetch tag, a prefetch request that is associated with a prefetch instruction that is executed by a remote processor. The one or more processors generate the prefetch request in a remote processor according to a prefetch protocol. The prefetch request includes i) a description of at least one prefetch request operation and ii) a prefetch request information. A local processor, of the one or more processors, receives the prefetch request from the remote processor.Type: GrantFiled: November 10, 2015Date of Patent: November 12, 2019Assignee: International Business Machines CorporationInventors: Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
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Patent number: 10474577Abstract: Enabling a prefetch request to be controlled in response to conditions in a receiver of the prefetch request and to conditions in a source of the prefetch request. One or more processors identify, based on a prefetch tag, a prefetch request that is associated with a prefetch instruction that is executed by a remote processor. The one or more processors generate the prefetch request in a remote processor according to a prefetch protocol. The prefetch request includes i) a description of at least one prefetch request operation and ii) a prefetch request information. A local processor, of the one or more processors, receives the prefetch request from the remote processor.Type: GrantFiled: June 20, 2016Date of Patent: November 12, 2019Assignee: International Business Machines CorporationInventors: Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
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Publication number: 20190332383Abstract: A method, system, and computer program product are provided for prioritizing prefetch instructions. The method includes a processor issuing a prefetch instruction and fetching elements from a cache that can include a memory or a higher level cache. The processor stores the elements in temporary storage and monitors for accesses by an instruction. The processor stores a record representing the prefetch instruction. The processor updates the record with an indicator and issues a new prefetch instruction by comparing the new prefetch instruction to the record, based on the new prefetch instruction matching the prefetch instruction, assigning the indicator to the new prefetch instruction as a priority value, based on the new prefetch instruction not matching the prefetch instruction, assigning a default value to the new prefetch instruction as the priority value, and determining whether to execute the new prefetch instruction, based on the priority value of the new prefetch instruction.Type: ApplicationFiled: June 18, 2019Publication date: October 31, 2019Inventors: Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum
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Publication number: 20190324758Abstract: A reload multiple instruction is used to restore a set of architected registers saved by a spill multiple instruction. The reload multiple instruction is executed, and the executing includes determining the set of architected registers to be restored, which is specified by the reload multiple instruction. The set of architected registers is restored from a selected snapshot that maps architected registers to physical registers. The restoring replaces one or more physical registers currently assigned to one or more architected registers of the set of architected registers with one or more physical registers of the selected snapshot corresponding to the set of architected registers.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel
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Patent number: 10452395Abstract: A query is performed to obtain cache residency and/or other information regarding selected data. The data to be queried is data of a cache line, prefetched or otherwise. The capability includes a Query Cache instruction that obtains cache residency information and/or other information and returns an indication of the requested information.Type: GrantFiled: July 20, 2016Date of Patent: October 22, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dan F. Greiner, Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel
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Publication number: 20190317768Abstract: A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.Type: ApplicationFiled: June 28, 2019Publication date: October 17, 2019Inventors: Dan F. Greiner, Christian Jacobi, Volodymyr Paprotski, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel
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Publication number: 20190303157Abstract: A method, system, and computer program product are provided for prioritizing prefetch instructions. The method includes a processor issuing a prefetch instruction and fetching elements from a cache that can include a memory or a higher level cache. The processor stores the elements in temporary storage and monitors for accesses by an instruction. The processor stores a record representing the prefetch instruction. The processor updates the record with an indicator and issues a new prefetch instruction by comparing the new prefetch instruction to the record, based on the new prefetch instruction matching the prefetch instruction, assigning the indicator to the new prefetch instruction as a priority value, based on the new prefetch instruction not matching the prefetch instruction, assigning a default value to the new prefetch instruction as the priority value, and determining whether to execute the new prefetch instruction, based on the priority value of the new prefetch instruction.Type: ApplicationFiled: June 18, 2019Publication date: October 3, 2019Inventors: Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum
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Patent number: 10430194Abstract: A method for managing tasks in a computer system comprising a processor and a memory, the method includes performing a first task by the processor, the first task comprising task-relating branch instructions and task-independent branch instructions and executing the branch prediction method, the execution resulting in task-relating branch prediction data in the branch prediction history table. In response to determining that the first task is to be interrupted or terminated, the method includes storing the task-relating branch prediction data of the first task in the task structure of the first task. In response to determining that a second task is to be continued, the method includes reading task-relating branch prediction data of the second task from the task structure of the second task, storing the task-relating branch prediction data of the second task in the branch prediction history table, and ensuring that task-independent branch prediction data is maintained.Type: GrantFiled: March 10, 2016Date of Patent: October 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wolfgang Gellerich, Peter M. Held, Martin Schwidefsky, Chung-Lung K. Shum
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Patent number: 10423418Abstract: A method for managing tasks in a computer system comprising a processor and a memory, the method includes performing a first task by the processor, the first task comprising task-relating branch instructions and task-independent branch instructions and executing the branch prediction method, the execution resulting in task-relating branch prediction data in the branch prediction history table. In response to determining that the first task is to be interrupted or terminated, the method includes storing the task-relating branch prediction data of the first task in the task structure of the first task. In response to determining that a second task is to be continued, the method includes reading task-relating branch prediction data of the second task from the task structure of the second task, storing the task-relating branch prediction data of the second task in the branch prediction history table, and ensuring that task-independent branch prediction data is maintained.Type: GrantFiled: November 30, 2015Date of Patent: September 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wolfgang Gellerich, Peter M. Held, Martin Schwidefsky, Chung-Lung K. Shum
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Patent number: 10417126Abstract: A technique relates to enabling a multiprocessor computer system to make a non-coherent request for a cache line. A first processor core sends a non-coherent fetch to a cache. In response to a second processor core having exclusive ownership of the cache line in the cache, the first processor core receives a stale copy of the cache line in the cache based on the non-coherent fetch. The non-coherent fetch is configured to obtain the stale copy for a predefined use. Cache coherency is maintained for the cache, such that the second processor core continues to have exclusive ownership of the cache line while the first processor core receives the stale copy of the cache line.Type: GrantFiled: November 8, 2017Date of Patent: September 17, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jane H. Bartik, Nicholas C. Matsakis, Chung-Lung K. Shum, Craig R. Walters
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Patent number: 10379862Abstract: A method, system, and computer program product are provided for prioritizing prefetch instructions. The method includes a processor issuing a prefetch instruction and fetching elements from a cache that can include a memory or a higher level cache. The processor stores the elements in temporary storage and monitors for accesses by an instruction. The processor stores a record representing the prefetch instruction. The processor updates the record with an indicator and issues a new prefetch instruction by comparing the new prefetch instruction to the record, based on the new prefetch instruction matching the prefetch instruction, assigning the indicator to the new prefetch instruction as a priority value, based on the new prefetch instruction not matching the prefetch instruction, assigning a default value to the new prefetch instruction as the priority value, and determining whether to execute the new prefetch instruction, based on the priority value of the new prefetch instruction.Type: GrantFiled: June 28, 2016Date of Patent: August 13, 2019Assignee: International Business Machines CorporationInventors: Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum
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Patent number: 10372611Abstract: Modifying prefetch request processing. A prefetch request is received by a local computer from a remote computer. The local computer responds to a determination that execution of the prefetch request is predicted to cause an address conflict during an execution of a transaction of the local processor by comparing a priority of the prefetch request with a priority of the transaction. Based on a result of the comparison, the local computer modifies program instructions that govern execution of the program instructions included in the prefetch request to include program instruction to perform one or both of: (i) a quiesce of the prefetch request prior to execution of the prefetch request, and (ii) a delay in execution of the prefetch request for a predetermined delay period.Type: GrantFiled: October 30, 2018Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
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Patent number: 10372457Abstract: A method, system, and computer program product are provided for prioritizing prefetch instructions. The method includes a processor issuing a prefetch instruction and fetching elements from a cache that can include a memory or a higher level cache. The processor stores the elements in temporary storage and monitors for accesses by an instruction. The processor stores a record representing the prefetch instruction. The processor updates the record with an indicator and issues a new prefetch instruction by comparing the new prefetch instruction to the record, based on the new prefetch instruction matching the prefetch instruction, assigning the indicator to the new prefetch instruction as a priority value, based on the new prefetch instruction not matching the prefetch instruction, assigning a default value to the new prefetch instruction as the priority value, and determining whether to execute the new prefetch instruction, based on the priority value of the new prefetch instruction.Type: GrantFiled: November 3, 2017Date of Patent: August 6, 2019Assignee: international Business Machines CorporationInventors: Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum
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Publication number: 20190236012Abstract: In a transactional memory environment including a first processor and one or more additional processors, a computer-implemented method includes identifying a memory location and sending a probe request from the first processor to the additional processors. The probe request includes the memory location. The computer implemented method further includes generating, by each additional processor, an indication including whether the memory location is in use for a transaction by the additional processor. The computer-implemented method further includes sending the indication from each additional processor to the first processor and proceeding, by the first processor, based on the indication.Type: ApplicationFiled: April 10, 2019Publication date: August 1, 2019Inventors: Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
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Patent number: 10365927Abstract: Embodiments relate to non-default instruction handling within a transaction. An aspect includes entering a transaction, the transaction comprising a first plurality of instructions and a second plurality of instructions, wherein a default manner of handling of instructions in the transaction is one of atomic and non-atomic. Another aspect includes encountering a non-default specification instruction in the transaction, wherein the non-default specification instruction comprises a single instruction that specifies the second plurality of instructions of the transaction for handling in a non-default manner comprising one of atomic and non-atomic, wherein the non-default manner is different from the default manner. Another aspect includes handling the first plurality of instructions in the default manner. Yet another aspect includes handling the second plurality of instructions in the non-default manner.Type: GrantFiled: November 9, 2017Date of Patent: July 30, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz, Valentina Salapura, Chung-Lung K. Shum
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Patent number: 10346197Abstract: In a transactional memory environment, a computer-implemented method includes a first processor initiating a first transaction and encountering an abort condition. Responsive to the abort condition, an abort other request is communicated between the first processor and one or more additional processors. The one or more additional processors receive the abort other request, and, responsive to the abort other request, the one or more additional processors selectively abort a current second transaction based on the abort other request and an abort other condition. Optionally, the transactional memory environment supports a transaction category scheme, whereby each transaction has associated therewith a category identifier. In such embodiments, the abort other request includes an abort category identifier, and the abort other condition includes aborting the current second transaction if the abort category identifier matches the category identifier for the current second transaction.Type: GrantFiled: August 18, 2016Date of Patent: July 9, 2019Assignee: International Business Machines CorporationInventors: Fadi Y. Busaba, Valentina Salapura, Chung-Lung K. Shum
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Patent number: 10346305Abstract: In a transactional memory environment including a first processor and one or more additional processors, a computer-implemented method includes identifying a memory location and sending a probe request from the first processor to the additional processors. The probe request includes the memory location. The computer implemented method further includes generating, by each additional processor, an indication including whether the memory location is in use for a transaction by the additional processor. The computer-implemented method further includes sending the indication from each additional processor to the first processor and proceeding, by the first processor, based on the indication.Type: GrantFiled: October 13, 2016Date of Patent: July 9, 2019Assignee: International Business Machines CorporationInventors: Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
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Patent number: 10339049Abstract: A garbage collection facility is provided for memory management within a computer. The facility implements, in part, grouping of infrequently accessed data units in a designated transient memory area, and includes designating an area of the memory as a transient memory area and an area as a conventional memory area, and counting, for each data unit in the transient or conventional memory areas a number of accesses to the data unit. The counting provides a respective access count for each data unit. For each data unit in the transient memory area or the conventional memory area, a determination is made whether the respective access count is below a transient threshold ascertained to separate frequently accessed data units and infrequently used data units. Data units with respective access counts below the transient threshold are grouped together as transient data units within the transient memory area.Type: GrantFiled: November 22, 2017Date of Patent: July 2, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Giles R. Frazier, Michael K. Gschwind, Christian Jacobi, Younes Manton, Anthony Saporito, Chung-Lung K. Shum
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Transactional memory system including cache versioning architecture to implement nested transactions
Patent number: 10331565Abstract: A computer system includes transactional memory to implement a nested transaction. The computer system generates a plurality of speculative identification numbers (IDs), identifies at least one of a software thread executed by a hardware processor and a memory operation performed in accordance with an application code. The computer system assigns at least one speculative cache version to a requested transaction based on a corresponding software thread. The speculative ID of the corresponding software thread identifies the speculative cache version. The computer system also identifies a nested transaction in the memory unit, assigns a cache version to the nested transaction, detects a conflict with the nested transaction, determines a conflicted nesting level of the nested transaction, and determines a cache version corresponding to the conflicted nesting level. The computer system also invalidates the cache version corresponding to the conflicted nesting level.Type: GrantFiled: May 31, 2016Date of Patent: June 25, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum -
Publication number: 20190187989Abstract: A data processor comprising a plurality of registers, and instruction execution circuitry having an associated instruction set, wherein the instruction set includes an instruction specifying at least a mask operand, a register operand and an immediate value operand, and the instruction execution circuitry, in response to an instance of the instruction, determines a Boolean value based on the mask operand and sets a respective one of a plurality of registers specified by the register operand of the instance to a value of the immediate value operand if the Boolean value is true. The instruction execution circuitry, in response to the instance of the instruction, may set the respective one of the plurality of registers specified by the register operand of the instance to zero if the Boolean value is false.Type: ApplicationFiled: February 21, 2019Publication date: June 20, 2019Inventors: Wolfgang Gellerich, Martin Schwidefsky, Chung-Lung K. Shum, Kai Weber