Abstract: Disclosed herein are an apparatus and a method for warning of vehicle collision. The positioning and state-reporting signal of a present vehicle is sensed and that of a target vehicle received. The signals are respectively converted to velocities. The relative velocity of the vehicles and the relative position of the vehicles after a time interval are obtained. The driver of the present vehicle is warned when the normal distance from the present vehicle to the line indicating the direction of the relative velocity is determined to be at a minimum and not greater than a warning distance.

Abstract: A successive approximation register analog-to-digital converter (SAR ADC) includes a comparator coupled to receive a sampled input voltage; a pair of arrays each including individually switchable binary-weighted capacitors that are switchably coupled to an output of the comparator via phase switches, respectively. A phase signal for controlling a corresponding phase switch associated with a current bit becomes asserted when a preceding bit finishes comparison, and the phase signal becomes de-asserted when the current bit finishes comparison.

Abstract: A method for transmitting data stream includes the steps of analyzing a request to generate a transmitting command, calculating a data receiving ability of a receiving end when receiving the transferring command, calculating an I frame dividing rate, a P frame dividing rate, and a B frame dividing rate based on the data receiving ability, dividing an I frame, a P frame, and a B frame based on the I frame dividing rate, the P frame dividing rate, and the B frame dividing rate to generate a plurality of I frame segments, P frame segments, and B frame segments, transmitting the I frame segments, P frame segments, and B frame segments of the data stream to the receiving end in turn base on the data receiving ability.

Abstract: A transmission control method for a vehicular ad hoc network system having a plurality of mobile nodes is provided. The mobile nodes include a source node, a destination node, and a plurality of relay nodes. The source node transmits a data packet to the destination node through the relay nodes. The method includes each mobile node capturing mobility information being periodically broadcasted from neighboring mobile nodes to correspondingly update the connection state table thereof, wherein the connection state table records the coverage remaining time between the mobile node and neighboring mobile nodes; when any of relay nodes determines that the coverage remaining time between the relay node and the subsequent mobile node is less than a predefined threshold, the relay node transforms into a proxy node, stores the data packet, and establishes a reliable sub-connection between the proxy node and a next proxy node or the destination node.

Abstract: A method for transmitting data stream includes the steps of analyzing a request to generate a transmitting command, calculating a data receiving ability of a receiving end when receiving the transferring command, calculating an I frame dividing rate, a P frame dividing rate, and a B frame dividing rate based on the data receiving ability, dividing an I frame, a P frame, and a B frame based on the I frame dividing rate, the P frame dividing rate, and the B frame dividing rate to generate a plurality of I frame segments, P frame segments, and B frame segments, transmitting the I frame segments, P frame segments, and B frame segments of the data stream to the receiving end in turn base on the data receiving ability.

Abstract: A method for a successive approximation register ADC which includes at least one capacitor array and a plurality of switches is provided, in which the capacitors of the capacitor array are one-to-one corresponding to the switches. The method includes the following steps: firstly, at least one multiplexer is configured. Then, a first comparison voltage is outputted based on the terminal voltages on the terminals of the capacitor array, and a comparison result is outputted according to the first comparison voltage and a second comparison voltage. Afterwards, a sequence of comparisons is controlled based on the comparison result to enter into a sequence of comparison phases. Finally, the switches are orderly selected, by the multiplexer based on the comparison phases, to switch directly according to the comparison result.

Abstract: A clock and data recovery (CDR) architecture which includes a frequency detector, a phase detector, a phase charge pump circuit, a frequency charge pump circuit and a voltage controlled oscillator is provided. The phase detector is configured to only include four AND gates to receive and evaluate the intermediate signals, generated by the frequency detector, and accordingly generate a phase control signal. The voltage controlled oscillator is configured to output a plurality of clock signals with different phases according to the current signals outputted from the phase and frequency charge pump circuits, and select at least one of the plurality of clock signals with different phases for sampling a data signal.

Abstract: A clock and data recovery (CDR) architecture which includes a frequency detector, a phase detector, a phase charge pump circuit, a frequency charge pump circuit and a voltage controlled oscillator is provided. The phase detector is configured to only include four AND gates to receive and evaluate the intermediate signals, generated by the frequency detector, and accordingly generate a phase control signal. The voltage controlled oscillator is configured to output a plurality of clock signals with different phases according to the current signals outputted from the phase and frequency charge pump circuits, and select at least one of the plurality of clock signals with different phases for sampling a data signal.

Abstract: A method for a successive approximation register ADC which includes at least one capacitor array and a plurality of switches is provided, in which the capacitors of the capacitor array are one-to-one corresponding to the switches. The method includes the following steps: firstly, at least one multiplexer is configured. Then, a first comparison voltage is outputted based on the terminal voltages on the terminals of the capacitor array, and a comparison result is outputted according to the first comparison voltage and a second comparison voltage. Afterwards, a sequence of comparisons is controlled based on the comparison result to enter into a sequence of comparison phases. Finally, the switches are orderly selected, by the multiplexer based on the comparison phases, to switch directly according to the comparison result.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window.

Abstract: A memory cell includes a pair of sub-cells, each including an access transistor, a storage transistor, and an isolation transistor that are serially coupled in sequence with their source/drain connected. The isolation transistor is shared with a sub-cell of an adjacent memory cell and always turned off, wherein the storage transistor is always turned on. A wordline is coupled to a gate of the access transistor of each sub-cell, and complementary bit lines are respectively coupled to sources/drains of the access transistors of the pair of sub-cells, such that data bit may be accessed between the bit line and the corresponding storage transistor through the corresponding access transistor.

Abstract: A collision detecting method, an electronic device, and a computer program product thereof are provided for the electronic device having an accelerometer, a positioning module, and a communication module. The method includes obtaining a plurality of acceleration variations within each of a plurality of sampling intervals respectively detected by the accelerometer. The method also includes transforming the corresponding acceleration variations into a plurality of frequency domain signals for each sampling interval, and calculating energy and entropy of the frequency domain signals. The method further includes determining a collision has occurred if the energy and the entropy corresponding to each of a plurality of specific sampling intervals among the sampling intervals both drastically increase then drastically decrease suddenly.

Abstract: An electrical-overstress (EOS) protection circuit for an electronic device includes series-connected resistors, a mode-control switch, and a bias circuit. The series-connected resistors are electrically coupled between an input and an output, and the mode-control switch is electrically coupled between the output and a ground. The bias circuit is electrically coupled to the input for generating a mode-control signal to control the mode-control switch. The bias circuit generates the mode-control signal in a way such that the mode-control switch is open in a normal mode and closed in an EOS mode.

Abstract: A memory cell includes a pair of sub-cells, each including an access transistor, a storage transistor, and an isolation transistor that are serially coupled in sequence with their source/drain connected. The isolation transistor is shared with a sub-cell of an adjacent memory cell and always turned off, wherein the storage transistor is always turned on. A wordline is coupled to a gate of the access transistor of each sub-cell, and complementary bit lines are respectively coupled to sources/drains of the access transistors of the pair of sub-cells, such that data bit may be accessed between the bit line and the corresponding storage transistor through the corresponding access transistor.

Abstract: An electrical-overstress (EOS) protection circuit for an electronic device includes series-connected resistors, a mode-control switch, and a bias circuit. The series-connected resistors are electrically coupled between an input and an output, and the mode-control switch is electrically coupled between the output and a ground. The bias circuit is electrically coupled to the input for generating a mode-control signal to control the mode-control switch. The bias circuit generates the mode-control signal in a way such that the mode-control switch is open in a normal mode and closed in an EOS mode.

Abstract: A process apparatus, a data scheduling method, and a computer readable medium thereof for a data schedule are provided. The process apparatus comprises a storage, a receiving interface, and a microprocessor. The microprocessor is respectively electrically connected to the storage and the receiving interface. The storage is configured to store a data scheduling structure which is constructed of a plurality of data items in an execution sequence. The receiving interface receives an input data item. The microprocessor retrieves at least one relevant data item from the data items according to the correlation information of the input data item. The microprocessor further performs a weight calculation according to the at least one relevant data item and the input data item, so as to generate at least one weight calculation result.

Abstract: A data relay mobile apparatus and a data relay method for a wireless network and a computer program product thereof are provided. The wireless network comprises a first mobile node and a second mobile node. The data relay mobile apparatus receives first status information and second status information from the first mobile node and the second mobile node, respectively. The data relay apparatus relays data according to the first status information and the second status information. With the aforesaid method, the present invention can effectively reduce the problems caused from shadow fading.

Abstract: An electrical-overstress (EOS) protection circuit for an electronic device includes series-connected resistors, a mode-control switch, and a bias circuit. The series-connected resistors are electrically coupled between an input and an output, and the mode-control switch is electrically coupled between the output and a ground. The bias circuit is electrically coupled to the input for generating a mode-control signal to control the mode-control switch. The bias circuit generates the mode-control signal in a way such that the mode-control switch is open in a normal mode and closed in an EOS mode.

Abstract: A metal oxide semiconductor device comprising a substrate, at least an isolation structure, a deep N-type well, a P-type well, a gate, a plurality of N-type extension regions, an N-type drain region, an N-type source region and a P-type doped region is provided. The N-type extension regions are disposed in the substrate between the isolation structures and either side of the gate, while the N-type drain region and the N-type source region are respectively disposed in the N-type extension regions at both sides of the gate. The P-type well surrounds the N-type extension regions, and the P-type doped region is disposed in the P-type well of the substrate and is isolated from the N-type source region by the isolation structure.