Abstract: A method includes forming a first mandrel pattern and a second mandrel pattern. The first mandrel pattern includes at least first and second mandrels for a mandrel-spacer double patterning process. The second mandrel pattern includes at least a third mandrel inserted between the first and second mandrels. The first mandrel pattern and the second mandrel pattern include a same material. The first and second mandrels are merged together with the third mandrel to form a single pattern.

Abstract: A method of fabricating a semiconductor device includes generating at least one photomask based on a layout and forming a plurality of active patterns on a substrate, using the at least one photomask. The layout includes a plurality of first patterns that extend parallel to each other in a first direction on a low-density region of the layout and a plurality of second patterns that extend parallel to each other in the first direction on a high-density region of the layout. The forming of the plurality of active patterns includes using the first patterns and the second patterns of the layout to respectively form a plurality of first active patterns and a plurality of second active patterns on the substrate.

Abstract: A method includes forming a first mandrel pattern and a second mandrel pattern. The first mandrel pattern includes at least first and second mandrels for a mandrel-spacer double patterning process. The second mandrel pattern includes at least a third mandrel inserted between the first and second mandrels. The first mandrel pattern and the second mandrel pattern include a same material. The first and second mandrels are merged together with the third mandrel to form a single pattern.

Abstract: A semiconductor device includes a first active fin on a substrate; a second active fin on the substrate and separate from the first active fin; and a first fin stub on the substrate, wherein the first fin stub connects a first end of the first active fin and a first end of the second active fin, wherein the fin stub is lower than both the first and the second active fins in height, wherein from a top view the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.

Abstract: A semiconductor device includes a first active fin on a substrate; a second active fin on the substrate and separate from the first active fin; and a first fin stub on the substrate, wherein the first fin stub connects a first end of the first active fin and a first end of the second active fin, wherein the fin stub is lower than both the first and the second active fins in height, wherein from a top view the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.

Abstract: A semiconductor device includes a first active fin on a substrate; a second active fin on the substrate and separate from the first active fin; a first fin stub on the substrate, wherein the first fin stub connects a bottom portion of the first active fin and a bottom portion of the second active fin; and an isolation feature over the first fin stub and between the first and second active fins. The first fin stub is lower than both the first and the second active fins in height. The isolation feature is higher than the first fin stub and lower than both the first and the second active fins in height. From a top view, the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.

Abstract: A semiconductor device is provided, which includes a substrate, a shallow trench isolation (STI), a gate dielectric structure, a capping structure and a gate structure. The STI is in the substrate and defines an active area of the substrate. The gate dielectric structure is on the active area. The capping structure is adjacent to the gate dielectric structure and at edges of the active area. The gate structure is on the gate dielectric structure and the capping structure. An equivalent oxide thickness of the capping structure is substantially greater than an equivalent oxide thickness of the gate dielectric structure.

Abstract: A semiconductor device includes a first active fin on a substrate; a second active fin on the substrate and separate from the first active fin; a first fin stub on the substrate, wherein the first fin stub connects a bottom portion of the first active fin and a bottom portion of the second active fin; and an isolation feature over the first fin stub and between the first and second active fins. The first fin stub is lower than both the first and the second active fins in height. The isolation feature is higher than the first fin stub and lower than both the first and the second active fins in height. From a top view, the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.

Abstract: A semiconductor device is provided, which includes a substrate, a shallow trench isolation (STI), a gate dielectric structure, a capping structure and a gate structure. The STI is in the substrate and defines an active area of the substrate. The gate dielectric structure is on the active area. The capping structure is adjacent to the gate dielectric structure and at edges of the active area. The gate structure is on the gate dielectric structure and the capping structure. An equivalent oxide thickness of the capping structure is substantially greater than an equivalent oxide thickness of the gate dielectric structure.

Abstract: A method includes receiving an integrated circuit design layout that includes first and second layout blocks separated by a first space. The first and second layout blocks include, respectively, first and second line patterns oriented lengthwise in a first direction. The method further includes adding a dummy pattern to the first space, which connects the first and second line patterns. The method further includes outputting a mandrel pattern layout and a cut pattern layout in a computer-readable format. The mandrel pattern layout includes the first and second line patterns and the dummy pattern. The cut pattern layout includes a pattern corresponding to the first space. In embodiments, the method further includes manufacturing a first mask with the mandrel pattern layout and manufacturing a second mask with the cut pattern layout. In embodiments, the method further includes patterning a substrate with the first mask and the second mask.

Abstract: A method includes receiving an integrated circuit design layout that includes first and second layout blocks separated by a first space. The first and second layout blocks include, respectively, first and second line patterns oriented lengthwise in a first direction. The method further includes adding a dummy pattern to the first space, which connects the first and second line patterns. The method further includes outputting a mandrel pattern layout and a cut pattern layout in a computer-readable format. The mandrel pattern layout includes the first and second line patterns and the dummy pattern. The cut pattern layout includes a pattern corresponding to the first space. In embodiments, the method further includes manufacturing a first mask with the mandrel pattern layout and manufacturing a second mask with the cut pattern layout. In embodiments, the method further includes patterning a substrate with the first mask and the second mask.

Abstract: A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.

Abstract: A fixing structure for a metal unit and a plastic unit includes a metal unit, a metal engagement portion, a plastic unit and a plastic engagement portion. The metal unit has a metal main body and a base body formed on one side of the metal main body. The metal engagement portion is a metal body fixed by welding to the base body of the metal unit. The plastic unit has a plastic main body. The plastic engagement portion is integrally formed as one piece on the plastic main body. The plastic unit is accommodated in the metal main body of the metal unit, and the metal engagement portion and the plastic engagement portion are mutually engaged. Aesthetics is increased and thermal cycle tests can be passed.

Abstract: A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.

Abstract: A wireless ear-hook headset includes a flexible tube, a receiver and a transceiver. The flexible tube has a cable, a first fixing binder fixed on one end of the cable, a second fixing binder fixed on the other end of the cable, and an outer layer. The cable has at least one shapeable metallic wire, a plurality of signal wires and an insulating cover layer. The outer layer has two ends which are fixedly connected with the first and second fixing binders respectively and fully covering the cable. The receiver is connected to the first fixing binder of the flexible tube. The transceiver is connected to the second fixing binder of the flexible tube. The present invention also discloses the flexible tube structure and a method for manufacturing the flexible tube.

Abstract: A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.

Abstract: A wireless ear-hook headset includes a flexible tube, a receiver and a transceiver. The flexible tube has a cable, a first fixing binder fixed on one end of the cable, a second fixing binder fixed on the other end of the cable, and an outer layer. The cable has at least one shapeable metallic wire, a plurality of signal wires and an insulating cover layer. The outer layer has two ends which are fixedly connected with the first and second fixing binders respectively and fully covering the cable. The receiver is connected to the first fixing binder of the flexible tube. The transceiver is connected to the second fixing binder of the flexible tube. The present invention also discloses the flexible tube structure and a method for manufacturing the flexible tube.

Abstract: A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension G; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness T substantially less than G/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process.

Abstract: A method of forming a integrated circuit pattern. The method includes coating a photoresist layer on a substrate; performing a lithography exposure process to the photoresist layer; performing a multiple-step post-exposure-baking (PEB) process to the photoresist layer; and developing the photoresist layer to form a patterned photoresist layer.

Abstract: A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.