Patents by Inventor Chung Nang Liu

Chung Nang Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11562909
    Abstract: Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: January 24, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Yu Lei, Xuesong Lu, Tae Hong Ha, Xianmin Tang, Andrew Nguyen, Tza-Jing Gung, Philip A. Kraus, Chung Nang Liu, Hui Sun, Yufei Hu
  • Publication number: 20220336223
    Abstract: Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.
    Type: Application
    Filed: June 22, 2022
    Publication date: October 20, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Yu Lei, Xuesong Lu, Tae Hong Ha, Xianmin Tang, Andrew Nguyen, Tza-Jing Gung, Philip A. Kraus, Chung Nang Liu, Hui Sun, Yufei Hu
  • Publication number: 20210366722
    Abstract: Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Yu Lei, Xuesong Lu, Tae Hong Ha, Xianmin Tang, Andrew Nguyen, Tza-Jing Gung, Philip A. Kraus, Chung Nang Liu, Hui Sun, Yufei Hu
  • Patent number: 9533332
    Abstract: Embodiments of the invention include methods for in-situ chamber dry cleaning a plasma processing chamber utilized for gate structure fabrication process in semiconductor devices. In one embodiment, a method for in-situ chamber dry clean includes supplying a first cleaning gas including at least a boron containing gas into a processing chamber in absence of a substrate disposed therein, supplying a second cleaning gas including at least a halogen containing gas into the processing chamber in absence of the substrate, and supplying a third cleaning gas including at least an oxygen containing gas into the processing chamber in absence of the substrate.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: January 3, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Noel Sun, Meihua Shen, Nicolas Gani, Chung Nang Liu, Radhika C. Mani
  • Publication number: 20130087174
    Abstract: Embodiments of the invention include methods for in-situ chamber dry cleaning a plasma processing chamber utilized for gate structure fabrication process in semiconductor devices. In one embodiment, a method for in-situ chamber dry clean includes supplying a first cleaning gas including at least a boron containing gas into a processing chamber in absence of a substrate disposed therein, supplying a second cleaning gas including at least a halogen containing gas into the processing chamber in absence of the substrate, and supplying a third cleaning gas including at least an oxygen containing gas into the processing chamber in absence of the substrate.
    Type: Application
    Filed: September 13, 2012
    Publication date: April 11, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Noel Sun, Meihua Shen, Nicolas Gani, Chung Nang Liu, Radhika C. Mani