Patents by Inventor Chung-Ren Lao

Chung-Ren Lao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200303441
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a light-collimating layer. The substrate has a plurality of pixels. The light-collimating layer is disposed on the substrate, and the light-collimating layer includes a transparent material layer, a first light-shielding layer, a second light-shielding layer and a plurality of transparent pillars. The transparent material layer covers the pixels. The first light-shielding layer is disposed on the substrate and the first light-shielding layer has a plurality of holes corresponding to the pixels. The second light-shielding layer is disposed on the first light-shielding layer. The transparent pillars are disposed in the second light-shielding layer.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chung-Ren LAO, Chih-Cherng LIAO, Shih-Hao LIU, Wu-Hsi LU, Ming-Cheng LO, Wei-Lun CHUNG, Chih-Wei LIN
  • Patent number: 10629726
    Abstract: The present disclosure provides a high-voltage semiconductor device, including: a substrate; an epitaxial layer disposed over the substrate and having a first conductive type; a gate structure disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate structure respectively; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. The present disclosure also provides a method for manufacturing the high-voltage semiconductor device.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 21, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chung-Ren Lao, Hsing-Chao Liu, Chu-Feng Chen, Wei-Chun Chou
  • Patent number: 10572070
    Abstract: An optical device is provided. The optical device includes a substrate including a plurality of pixel units, a dielectric layer disposed on the substrate, a patterned light-transmitting layer disposed on the dielectric layer and corresponding to the plurality of pixel units, and a plurality of continuous light-shielding layers disposed on the dielectric layer and located on both sides of the patterned light-transmitting layer. A method for fabricating an optical device is also provided.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: February 25, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Cherng Liao, Shih-Hao Liu, Wu-Hsi Lu, Ming-Cheng Lo, Chung-Ren Lao, Yun-Chou Wei, Yin Chen, Hsin-Hui Lee, Hsueh-Jung Lin, Wen-Chih Lu, Ting-Jung Lu
  • Publication number: 20190391701
    Abstract: An optical device is provided. The optical device includes a substrate including a plurality of pixel units, a dielectric layer disposed on the substrate, a patterned light-transmitting layer disposed on the dielectric layer and corresponding to the plurality of pixel units, and a plurality of continuous light-shielding layers disposed on the dielectric layer and located on both sides of the patterned light-transmitting layer. A method for fabricating an optical device is also provided.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Cherng LIAO, Shih-Hao LIU, Wu-Hsi LU, Ming-Cheng LO, Chung-Ren LAO, Yun-Chou WEI, Yin CHEN, Hsin-Hui LEE, Hsueh-Jung LIN, Wen-Chih LU, Ting-Jung LU
  • Patent number: 10395085
    Abstract: Embodiments of the disclosure relate to a semiconductor device. The semiconductor device includes a semiconductor substrate, a first metal wiring layer disposed on the semiconductor substrate, an interlayer dielectric layer (ILD) disposed on the first metal wiring layer, a second metal wiring layer disposed on the interlayer dielectric layer, and a first via and a second via disposed in the interlayer dielectric layer. The second via is on the first via, and there is not any metal wiring layer in the interlayer dielectric layer.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 27, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shih-Hao Liu, Leuh Fang, Chih-Cherng Liao, Yun-Chou Wei, Chung-Ren Lao, Wu-Hsi Lu
  • Publication number: 20190171857
    Abstract: Embodiments of the disclosure relate to a semiconductor device. The semiconductor device includes a semiconductor substrate, a first metal wiring layer disposed on the semiconductor substrate, an interlayer dielectric layer (ILD) disposed on the first metal wiring layer, a second metal wiring layer disposed on the interlayer dielectric layer, and a first via and a second via disposed in the interlayer dielectric layer. The second via is on the first via, and there is not any metal wiring layer in the interlayer dielectric layer.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 6, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shih-Hao LIU, Leuh Fang, Chih-Cherng Liao, Yun-Chou Wei, Chung-Ren Lao, Wu-Hsi Lu
  • Patent number: 9978861
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate having an isolation region and an active region defined by the isolation region. At least one trench is formed in the active region and extends along a first direction. A gate layer is disposed on the active region and extends along a second direction, wherein the gate layer conformably fills the at least one trench and covers a bottom surface and sidewalls of the at least one trench. The disclosure also provides a method for manufacturing the semiconductor device.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: May 22, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chung-Ren Lao, Hsing-Chao Liu, Chih-Jen Huang
  • Patent number: 9818861
    Abstract: A semiconductor device including a substrate having a drain region therein is provided. A gate-electrode layer is disposed on the drain region. A first field-plate conductor is disposed on the substrate and overlaps the drain region. A gap is located laterally between the first field-plate conductor and the gate-electrode layer. A second field-plate conductor covers the first field-plate conductor and the gap. The second field-plate conductor is separated from the first field-plate conductor. A method for forming the semiconductor device is also provided.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: November 14, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chien-Hsien Song, Chung-Ren Lao
  • Patent number: 9525020
    Abstract: A semiconductor device including a substrate having an isolation structure therein is disclosed. A capacitor is disposed on the isolation structure and includes a polysilicon electrode, an insulating layer disposed on the polysilicon electrode, and a metal electrode disposed on the insulating layer. A method for forming the semiconductor device is also disclosed.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: December 20, 2016
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chung-Ren Lao, Hsing-Chao Liu, Tzung-Hsian Wu, Chih-Jen Huang
  • Publication number: 20160315189
    Abstract: A semiconductor device including a substrate having a drain region therein is provided. A gate-electrode layer is disposed on the drain region. A first field-plate conductor is disposed on the substrate and overlaps the drain region. A gap is located laterally between the first field-plate conductor and the gate-electrode layer. A second field-plate conductor covers the first field-plate conductor and the gap. The second field-plate conductor is separated from the first field-plate conductor. A method for forming the semiconductor device is also provided.
    Type: Application
    Filed: April 24, 2015
    Publication date: October 27, 2016
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chien-Hsien SONG, Chung-Ren LAO
  • Publication number: 20160172490
    Abstract: The present disclosure provides a high-voltage semiconductor device, including: a substrate; an epitaxial layer disposed over the substrate and having a first conductive type; a gate structure disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate structure respectively; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. The present disclosure also provides a method for manufacturing the high-voltage semiconductor device.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 16, 2016
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chung-Ren LAO, Hsing-Chao LIU, Chu-Feng CHEN, Wei-Chun CHOU
  • Patent number: 9343572
    Abstract: A high-voltage semiconductor device is provided. The high-voltage semiconductor device includes a substrate; an epitaxial layer and a gate structure; a first conductive type first high-voltage well region and a second conductive type high-voltage well region disposed in the epitaxial layer at opposite sides of the gate structure respectively, wherein the first conductive type is different from the second conductive type; a source region and a drain region; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. A method for manufacturing the high-voltage semiconductor device is also provided.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: May 17, 2016
    Assignee: Vangaurd International Semiconductor Corporation
    Inventors: Chung-Ren Lao, Hsing-Chao Liu, Chu-Feng Chen, Wei-Chun Chou
  • Patent number: 9224862
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: December 29, 2015
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wei-Chun Chou, Yi-Hung Chiu, Chu-Feng Chen, Cheng-Yi Hsieh, Chung-Ren Lao
  • Publication number: 20150295018
    Abstract: A semiconductor device including a substrate having an isolation structure therein is disclosed. A capacitor is disposed on the isolation structure and includes a polysilicon electrode, an insulating layer disposed on the polysilicon electrode, and a metal electrode disposed on the insulating layer. A method for forming the semiconductor device is also disclosed.
    Type: Application
    Filed: April 10, 2014
    Publication date: October 15, 2015
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chung-Ren LAO, Hsing-Chao LIU, Tzung-Hsian WU, Chih-Jen HUANG
  • Publication number: 20150295032
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate having an isolation region and an active region defined by the isolation region. At least one trench is formed in the active region and extends along a first direction. A gate layer is disposed on the active region and extends along a second direction, wherein the gate layer conformably fills the at least one trench and covers a bottom surface and sidewalls of the at least one trench. The disclosure also provides a method for manufacturing the semiconductor device.
    Type: Application
    Filed: April 9, 2014
    Publication date: October 15, 2015
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chung-Ren LAO, Hsing-Chao LIU, Chih-Jen HUANG
  • Publication number: 20150054071
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Application
    Filed: August 26, 2014
    Publication date: February 26, 2015
    Inventors: Wei-Chun CHOU, Yi-Hung CHIU, Chu-Feng CHEN, Cheng-Yi HSIEH, Chung-Ren LAO
  • Patent number: 8847332
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: September 30, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wei-Chun Chou, Yi-Hung Chiu, Chu-Feng Chen, Cheng-Yi Hsieh, Chung-Ren Lao
  • Patent number: 8466019
    Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: June 18, 2013
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chu-Feng Chen, Chung-Ren Lao, Pai-Chun Kuo, Chien-Hsien Song, Hua-Chun Chiue, An-Hung Lin
  • Publication number: 20120267715
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Application
    Filed: April 20, 2011
    Publication date: October 25, 2012
    Inventors: Wei-Chun CHOU, Yi-Hung CHIU, Chu-Feng CHEN, Cheng-Yi HSIEH, Chung-Ren LAO
  • Publication number: 20120025308
    Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.
    Type: Application
    Filed: October 6, 2011
    Publication date: February 2, 2012
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR
    Inventors: Chu-Feng Chen, Chung-Ren Lao, Pai-Chun Kuo, Chien-Hsien Song, Hua-Chun Chiue, An-Hung Lin