Patents by Inventor Chung-Ren Lao

Chung-Ren Lao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8058121
    Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: November 15, 2011
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chu-Feng Chen, Chung-Ren Lao, Pai-Chun Kuo, Chien-Hsien Song, Hua-Chun Chiue, An-Hung Lin
  • Publication number: 20090321825
    Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.
    Type: Application
    Filed: June 29, 2009
    Publication date: December 31, 2009
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chu-Feng CHEN, Chung-Ren LAO, Pai-Chun KUO, Chien-Hsien SONG, Hua-Chun CHIUE, An-Hung LIN
  • Patent number: 7123303
    Abstract: A focal plane array in which information from the pixel forming elements is transferred into a vertical shift register and then from the last stage of the vertical shift registers row by row into a horizontal shift register is provided with a storage element and gate between each vertical register and the corresponding stage of the horizontal register. After the information currently in the storage gates has been transferred to the corresponding HCCD stages, the transfer gate is closed, and the next shift of the vertical registers begins, during a time when the vertical registers would otherwise be stopped, waiting for the multi-phase operation of the horizontal register. This time is used for usefully increasing the time for the vertical shift operation, and the clock is advantageously made slower. Alternatively, a faster frame rate can be handled by conventional clock circuits.
    Type: Grant
    Filed: April 14, 1994
    Date of Patent: October 17, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Ho-Ching Chien, Chun-Hui Tsai, Chung-Ren Lao