Abstract: A semiconductor memory apparatus including a memory cell array, a switch circuit, and a sensing circuit is provided. The memory cell array includes multiple memory cells. The switch circuit includes at least one switch. Each of the switch receives a control signal and is turned on or off under control of the control signal. When an erase verification is performed, the sensing circuit sequentially receives an erase verification current generated by each of the memory cells through the switch circuit to verify an erase state of the each of the memory cells.

Abstract: A memory and a sense amplifying device are provided. The sense amplifying device includes a differential amplifier, a first pre-charge circuit, and a control voltage generator. The differential amplifier has a first input terminal and a second input terminal to receive a data signal and a reference signal, respectively. The first pre-charge circuit is coupled to the first input terminal of the differential amplifier. The first pre-charge circuit, based on a power voltage, performs a pre-charge operation on the first input terminal of the differential amplifier according to a pre-charge enable signal and a control voltage. The control voltage generator generates the control voltage according to the power voltage, and the control voltage and the power voltage are in a positive correlation.

Abstract: A power-on read circuit includes a power voltage detector, a first voltage booster, a voltage selector, a reference voltage generator and a read voltage generator. The power voltage detector detects a power voltage to generate a control signal. The first voltage booster generates a first boosted voltage according to the control signal. The voltage selector selects the power voltage or the first boosted voltage to generate a selected voltage. The reference voltage generator receives the selected voltage as an operating power source, and generates a reference voltage based on the selected voltage according to the control signal. The read voltage generator generates a second boosted voltage according to the reference voltage and a clock signal, and generate a read voltage based on the second boosted voltage according to the control signal. The read voltage is provided to a memory cell array to perform a data reading operation.

Abstract: A semiconductor memory apparatus including a memory cell array, a switch circuit, and a sensing circuit is provided. The memory cell array includes multiple memory cells. The switch circuit includes at least one switch. Each of the switch receives a control signal and is turned on or off under control of the control signal. When an erase verification is performed, the sensing circuit sequentially receives an erase verification current generated by each of the memory cells through the switch circuit to verify an erase state of the each of the memory cells.

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal

Abstract: A word line decoder circuit located in a memory storage apparatus is provided. The memory storage apparatus includes a memory cell array. The word line decoder circuit includes a word line decoder and a power supply circuit. The word line decoder is coupled to a plurality of word lines of the memory storage apparatus. The power supply circuit is coupled to the word line decoder. The power supply circuit is configured to provide a first power to the word line decoder in a read mode, and provide a second power to the word line decoder in a standby mode. A voltage value of the first power is greater than or less than that of the second power.

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract: A flash memory storage apparatus having a plurality of operation modes is provided. The flash memory storage apparatus includes a memory controller circuit and a memory cell array. The memory controller circuit is configured to control the flash memory storage apparatus to operate in one of the operation modes. The operation modes include a low standby current mode. The memory cell array is coupled to the memory controller circuit. The memory cell array is configured to store data. The data includes read-only memory data. The memory controller circuit controls the flash memory storage apparatus to enter the low standby current mode according to a first command. The memory controller circuit wakes up the flash memory storage apparatus from the low standby current mode according to a second command. When the flash memory storage apparatus operates in the low standby current mode, the read-only memory data is kept.

Abstract: A voltage level shifter including a voltage level shifting circuit and a boost circuit is provided. The voltage level shifting circuit includes a first reference input end, a second reference input end, a first boosted input end, and a second boosted input end. The voltage level shifting circuit operates between a first voltage and a second voltage. The boost circuit is coupled to the voltage level shifting circuit. The boost circuit boosts the first boosted input end and the second boosted input end according to voltage values of the first reference input end and the second reference input end to reduce a transient current that flows from the first voltage to the second voltage.

Abstract: A word line decoder circuit located in a memory storage apparatus is provided. The memory storage apparatus includes a memory cell array. The word line decoder circuit includes a word line decoder and a power supply circuit. The word line decoder is coupled to a plurality of word lines of the memory storage apparatus. The power supply circuit is coupled to the word line decoder. The power supply circuit is configured to provide a first power to the word line decoder in a read mode, and provide a second power to the word line decoder in a standby mode. A voltage value of the first power is greater than or less than that of the second power.

Abstract: A flash memory storage apparatus having a plurality of operation modes is provided. The flash memory storage apparatus includes a memory controller circuit and a memory cell array. The memory controller circuit is configured to control the flash memory storage apparatus to operate in one of the operation modes. The operation modes include a low standby current mode. The memory cell array is coupled to the memory controller circuit. The memory cell array is configured to store data. The data includes read-only memory data. The memory controller circuit controls the flash memory storage apparatus to enter the low standby current mode according to a first command. The memory controller circuit wakes up the flash memory storage apparatus from the low standby current mode according to a second command. When the flash memory storage apparatus operates in the low standby current mode, the read-only memory data is kept.

Abstract: A voltage level shifter including a voltage level shifting circuit and a boost circuit is provided. The voltage level shifting circuit includes a first reference input end, a second reference input end, a first boosted input end, and a second boosted input end. The voltage level shifting circuit operates between a first voltage and a second voltage. The boost circuit is coupled to the voltage level shifting circuit. The boost circuit boosts the first boosted input end and the second boosted input end according to voltage values of the first reference input end and the second reference input end to reduce a transient current that flows from the first voltage to the second voltage.

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal

Abstract: An exemplary embodiment of the present disclosure provides a programming voltage generator for a nonvolatile memory device. The programming voltage generator comprises a power circuit, a detector, a switching circuit, a control signal generator, and a regulation circuit. The power circuit outputs a programming voltage according to a voltage control signal. The detector detects whether the programming voltage is larger than or equal to a breakdown voltage of the nonvolatile memory device, so as to output an indication signal. The switching circuit temporally drops the programming voltage according to the indication signal. The control signal generator generates a plurality of regulation control signals. The regulation circuit generates the voltage control signal according to the programming voltage and the regulation control signals.

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Abstract: A voltage regulator including an over-drive circuit and a control circuit is illustrated. The over-drive circuit receives a first voltage signal output from a sensing amplifier in a DRAM circuit, and regulates the first voltage signal according to an over-drive signal. The a control circuit electrically connected to the over-drive circuit receives a sense signal, and outputs the over-drive signal according to the sense signal, wherein the sense signal is asserted when a bit line in the DRAM circuit is sensed that an restoring and operation is performed. The over-drive signal goes down to a level of a second voltage signal from a current level thereof dependent on an external power merely when the sense signal is asserted but has not been asserted for a delay time, or otherwise, the over-drive signal is equal to the external power.

Abstract: A voltage regulator including an over-drive circuit and a control circuit is illustrated. The over-drive circuit receives a first voltage signal output from a sensing amplifier in a DRAM circuit, and regulates the first voltage signal according to an over-drive signal. The a control circuit electrically connected to the over-drive circuit receives a sense signal, and outputs the over-drive signal according to the sense signal, wherein the sense signal is asserted when a bit line in the DRAM circuit is sensed that an restoring and operation is performed. The over-drive signal goes down to a level of a second voltage signal from a current level thereof dependent on an external power merely when the sense signal is asserted but has not been asserted for a delay time, or otherwise, the over-drive signal is equal to the external power.