Patents by Inventor Claes H. Bjorkman
Claes H. Bjorkman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9502294Abstract: A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.Type: GrantFiled: November 8, 2013Date of Patent: November 22, 2016Assignee: Applied Materials, Inc.Inventors: Klaus Schuegraf, Seshadri Ramaswami, Michael R. Rice, Mohsen S. Salek, Claes H. Bjorkman
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Publication number: 20140196850Abstract: A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.Type: ApplicationFiled: November 8, 2013Publication date: July 17, 2014Applicant: APPLIED MATERIALS, INC.Inventors: Klaus Schuegraf, Seshadri Ramaswami, Michael R. Rice, Mohsen S. Salek, Claes H. Bjorkman
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Patent number: 8580615Abstract: A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.Type: GrantFiled: February 17, 2012Date of Patent: November 12, 2013Assignee: Applied Materials, Inc.Inventors: Klaus Schuegraf, Seshadri Ramaswami, Michael R. Rice, Mohsen S. Salek, Claes H. Bjorkman
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Publication number: 20130045570Abstract: A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.Type: ApplicationFiled: February 17, 2012Publication date: February 21, 2013Applicant: Applied Materials, Inc.Inventors: Klaus Schuegraf, Seshadri Ramaswami, Michael R. Rice, Mohsen S. Salek, Claes H. Bjorkman
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Patent number: 7458335Abstract: A magnetic field-enhanced plasma reactor is disclosed, comprising a reaction chamber for applying a plasma to a substrate, a plurality of primary electromagnets disposed about said reaction chamber, and a plurality of secondary electromagnets. At least two of the primary electromagnets are adjacent to each other, and each of these primary electromagnets has at least one secondary electromagnet disposed within a region defined by a right rectangular prism having the largest perimeter that fits within the outer perimeter of the primary magnet. Typically, at least one of the secondary electromagnets in one of the at least two adjacent primary electromagnets is itself adjacent to a secondary electromagnet disposed in the other of the at least two adjacent primary electromagnets. This arrangement is found to eliminate non-uniformities observed at regions of the substrate which are disposed closest to the vertices formed by the adjacent primary electromagnets.Type: GrantFiled: October 10, 2002Date of Patent: December 2, 2008Assignee: Applied Materials, Inc.Inventor: Claes H. Bjorkman
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Publication number: 20080283387Abstract: In a first aspect, a programmable transfer device is provided for transferring conductive pieces to electrode pads of a target substrate. The programmable transfer device includes (1) a transfer substrate; and (2) a plurality of individually addressable electrodes formed on the transfer substrate. Each electrode is adapted to selectively attract and hold a conductive piece during transfer of the conductive piece to an electrode pad of a target substrate. Numerous other aspects are provided.Type: ApplicationFiled: August 4, 2008Publication date: November 20, 2008Inventors: Michael R. Rice, Claes H. Bjorkman, Jun Zhao, Kenneth S. Collins, Thomas Miu
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Patent number: 7407081Abstract: In a first aspect, a programmable transfer device is provided for transferring conductive pieces to electrode pads of a target substrate. The programmable transfer device includes (1) a transfer substrate; and (2) a plurality of individually addressable electrodes formed on the transfer substrate. Each electrode is adapted to selectively attract and hold a conductive piece during transfer of the conductive piece to an electrode pad of a target substrate. Numerous other aspects are provided.Type: GrantFiled: March 31, 2005Date of Patent: August 5, 2008Assignee: Applied Materials, Inc.Inventors: Michael R. Rice, Claes H. Bjorkman, Jun Zhao, Kenneth S. Collins, Thomas Miu
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Patent number: 7227244Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.Type: GrantFiled: August 24, 2004Date of Patent: June 5, 2007Assignee: Applied Materials, Inc.Inventors: Claes H. Bjorkman, Melissa Min Yu, Hongquing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
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Patent number: 7105442Abstract: A method is described for decreasing the critical dimensions of integrated circuit features in which a first masking layer (101) is deposited, patterned and opened in the manner of typical feature etching, and a second masking layer (201) is deposited thereon prior to etching the underlying insulator. The second masking layer is advantageously coated in a substantially conformal manner. Opening the second masking layer while leaving material of the second layer on the sidewalls of the first masking layer as spacers leads to reduction of the feature critical dimension in the underlying insulator. Ashable masking materials, including amorphous carbon and organic materials are removable without CMP, thereby reducing costs. Favorable results are also obtained utilizing more than one masking layer (101, 301) underlying the topmost masking layer (302) from which the spacers are formed. Embodiments are also described in which slope etching replaces the addition of a separate spacer layer.Type: GrantFiled: May 22, 2002Date of Patent: September 12, 2006Assignee: Applied Materials, Inc.Inventors: Hongching Shan, Kenny L. Doan, Jingbao Liu, Michael S. Barnes, Hong D. Nguyen, Christopher Dennis Bencher, Christopher S. Ngai, Wendy H. Yeh, Eda Tuncel, Claes H. Bjorkman
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Patent number: 6949203Abstract: An integrated in situ etch process performed in a multichamber substrate processing system having first and second etching chambers. In one embodiment the first chamber includes an interior surface that has been roughened to at least 100 Ra and the second chamber includes an interior surface that has a roughness of less than about 32 Ra. The process includes transferring a substrate having formed thereon in a downward direction a patterned photoresist mask, a dielectric layer, a barrier layer and a feature in the substrate to be contacted into the first chamber where the dielectric layer is etched in a process that encourages polymer formation over the roughened interior surface of the chamber. The substrate is then transferred from the first chamber to the second chamber under vacuum conditions and, in the second chamber, is exposed to a reactive plasma such as oxygen to strip away the photoresist mask deposited over the substrate.Type: GrantFiled: March 3, 2003Date of Patent: September 27, 2005Assignee: Applied Materials, Inc.Inventors: Chang-Lin Hsieh, Diana Xiaobing Ma, Brian Sy Yuan Shieh, Gerald Zheyao Yin, Jennifer Sun, Senh Thach, Lee Luo, Claes H. Bjorkman
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Patent number: 6902947Abstract: Disclosed herein is a method of improving the adhesion of a hydrophobic self-assembled monolayer (SAM) coating to a surface of a MEMS structure, for the purpose of preventing stiction. The method comprises treating surfaces of the MEMS structure with a plasma generated from a source gas comprising oxygen and, optionally, hydrogen. The treatment oxidizes the surfaces, which are then reacted with hydrogen to form bonded OH groups on the surfaces. The hydrogen source may be present as part of the plasma source gas, so that the bonded OH groups are created during treatment of the surfaces with the plasma. Also disclosed herein is an integrated method for release and passivation of MEMS structures which may be adjusted to be carried out in a either a single chamber processing system or a multi-chamber processing system.Type: GrantFiled: May 9, 2003Date of Patent: June 7, 2005Assignee: Applied Materials, Inc.Inventors: Jeffrey D. Chinn, Rolf A. Guenther, Michael B. Rattner, James A. Cooper, Toi Yue Becky Leung, Claes H. Bjorkman
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Patent number: 6858153Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.Type: GrantFiled: November 5, 2001Date of Patent: February 22, 2005Assignee: Applied Materials Inc.Inventors: Claes H. Bjorkman, Min Melissa Yu, Hongquing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
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Patent number: 6793835Abstract: An integrated in situ etch process performed in a multichamber substrate processing system having first and second etching chambers. The process includes transferring a substrate having formed thereon in a downward direction a patterned photoresist mask, a dielectric layer, a stop layer and a feature in the substrate to be contacted into the first etching chamber to etch the dielectric layer. The substrate is then transferred from the first etching chamber to the second etching chamber under vacuum conditions and, in the second etching chamber, is exposed to an oxygen plasma or similar environment to strip away the photoresist mask deposited over the substrate. After the photoresist mask is stripped, the stop layer is etched through to the feature to be contacted in either the second or a third etching chamber of said multichamber substrate processing system. All three etching steps are performed in a system level in situ process so that the substrate is not exposed to an ambient between steps.Type: GrantFiled: October 24, 2002Date of Patent: September 21, 2004Inventors: Lee Luo, Claes H. Bjorkman, Brian Sy Yuan Shieh, Gerald Zheyao Yin
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Patent number: 6787475Abstract: A dielectric plasma etch method particularly useful for assuring that residue does not form in large open pad areas used for monitoring etching of narrow via and contact holes. The main dielectric etch of the via and contact holes uses a highly polymerizing chemistry, preferably of a low-F/C fluorocarbon such as C4F6 in conjunction with O2 and Ar. A short flash step precedes the main plasma etch using a plasma of a gas less polymerizing than the gas of the main etch, and the plasma is not extinguished between the flash and main steps. The flash step may be used to remove an anti-reflection coating (ARC) covering the dielectric layer and use a lean fluorocarbon, such as CF4, perhaps together with O2 and Ar. In the absence of ARC, an argon flash may be used.Type: GrantFiled: June 5, 2002Date of Patent: September 7, 2004Inventors: Zhuxu Wang, Jingbao Liu, Claes H. Bjorkman, Bryan Pu
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Publication number: 20040033639Abstract: Disclosed herein is a method of improving the adhesion of a hydrophobic self-assembled monolayer (SAM) coating to a surface of a MEMS structure, for the purpose of preventing stiction. The method comprises treating surfaces of the MEMS structure with a plasma generated from a source gas comprising oxygen and, optionally, hydrogen. The treatment oxidizes the surfaces, which are then reacted with hydrogen to form bonded OH groups on the surfaces. The hydrogen source may be present as part of the plasma source gas, so that the bonded OH groups are created during treatment of the surfaces with the plasma. Also disclosed herein is an integrated method for release and passivation of MEMS structures which may be adjusted to be carried out in a either a single chamber processing system or a multi-chamber processing system.Type: ApplicationFiled: May 9, 2003Publication date: February 19, 2004Applicant: APPLIED MATERIALS, INC.Inventors: Jeffrey D. Chinn, Rolf A. Guenther, Michael B. Rattner, James A. Cooper, Toi Yue Becky Leung, Claes H. Bjorkman
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Patent number: 6686293Abstract: Disclosed herein is a method of etching a trench in a silicon-containing dielectric material, in the absence of a trench etch-stop layer, where the silicon-containing dielectric material has a dielectric constant of about 4 or less. The method comprises exposing the dielectric material to a plasma generated from a source gas comprising a fluorine-containing etchant gas and an additive gas selected from the group consisting of carbon monoxide (CO), argon, and combinations thereof. A volumetric flow ratio of the additive gas to the fluorine-containing etchant gas is within the range of about 1.25:1 to about 20:1 (more typically, about 2.5:1 to about 20:1), depending on the particular fluorine-containing etchant gas used. The method provides good control over critical dimensions and etch profile during trench etching. Also disclosed herein is a method of forming a dual damascene structure, without the need for an intermediate etch stop layer.Type: GrantFiled: May 10, 2002Date of Patent: February 3, 2004Assignee: Applied Materials, IncInventors: Yunsang Kim, Kenny L. Doan, Claes H. Björkman, Hongqing Shan
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Patent number: 6669858Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.Type: GrantFiled: November 5, 2001Date of Patent: December 30, 2003Assignee: Applied Materials Inc.Inventors: Claes H. Bjorkman, Min Melissa Yu, Hongquing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
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Publication number: 20030219988Abstract: A method is described for decreasing the critical dimensions of integrated circuit features in which a first masking layer (101) is deposited, patterned and opened in the manner of typical feature etching, and a second masking layer (201) is deposited thereon prior to etching the underlying insulator. The second masking layer is advantageously coated in a substantially conformal manner. Opening the second masking layer while leaving material of the second layer on the sidewalls of the first masking layer as spacers leads to reduction of the feature critical dimension in the underlying insulator. Ashable masking materials, including amorphous carbon and organic materials are removable without CMP, thereby reducing costs. Favorable results are also obtained utilizing more than one masking layer (101, 301) underlying the topmost masking layer (302) from which the spacers are formed. Embodiments are also described in which slope etching replaces the addition of a separate spacer layer.Type: ApplicationFiled: May 22, 2002Publication date: November 27, 2003Applicant: Applied Materials, Inc.Inventors: Hongqing Shan, Kenny L. Doan, Jingbao Liu, Michael S. Barnes, Huong Thanh Nguyen, Christopher Dennis Bencher, Christopher S. Ngai, Wendy H. Yeh, Eda Tuncel, Claes H. Bjorkman
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Publication number: 20030211750Abstract: Disclosed herein is a method of etching a trench in a silicon-containing dielectric material, in the absence of a trench etch-stop layer, where the silicon-containing dielectric material has a dielectric constant of about 4 or less. The method comprises exposing the dielectric material to a plasma generated from a source gas comprising a fluorine-containing etchant gas and an additive gas selected from the group consisting of carbon monoxide (CO), argon, and combinations thereof. A volumetric flow ratio of the additive gas to the fluorine-containing etchant gas is within the range of about 1.25:1 to about 20:1 (more typically, about 2.5:1 to about 20:1), depending on the particular fluorine-containing etchant gas used. The method provides good control over critical dimensions and etch profile during trench etching. Also disclosed herein is a method of forming a dual damascene structure, without the need for an intermediate etch stop layer.Type: ApplicationFiled: May 10, 2002Publication date: November 13, 2003Inventors: Yunsang Kim, Kenny L. Doan, Claes H. Bjorkman, Hongqing Shan
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Publication number: 20030164354Abstract: An integrated in situ etch process performed in a multichamber substrate processing system having first and second etching chambers. In one embodiment the first chamber includes an interior surface that has been roughened to at least 100 Ra and the second chamber includes an interior surface that has a roughness of less than about 32 Ra. The process includes transferring a substrate having formed thereon in a downward direction a patterned photoresist mask, a dielectric layer, a barrier layer and a feature in the substrate to be contacted into the first chamber where the dielectric layer is etched in a process that encourages polymer formation over the roughened interior surface of the chamber. The substrate is then transferred from the first chamber to the second chamber under vacuum conditions and, in the second chamber, is exposed to a reactive plasma such as oxygen to strip away the photoresist mask deposited over the substrate.Type: ApplicationFiled: March 3, 2003Publication date: September 4, 2003Applicant: Applied Materials, Inc.Inventors: Chang-Lin Hsieh, Diana Xiaobing Ma, Brian Sy Yuan Shieh, Gerald Zheyao Yin, Jennifer Sun, Senh Thach, Lee Luo, Claes H. Bjorkman