Abstract: The method for producing a field effect transistor on a substrate comprising a support layer, a sacrificial layer and a semi-conducting layer comprises forming an active area in the semi-conducting layer. The active area is delineated by a closed peripheral insulation pattern and comprises an additional pattern made from insulating material. The method also comprises etching the insulating material of the additional pattern to access the sacrificial layer, etching the sacrificial layer resulting in formation of a first cavity, forming a dielectric layer on a top wall of the first cavity, and depositing an electrically conducting layer in the first cavity. The closed peripheral insulation pattern is formed through the semi-conducting layer and the sacrificial layer.

Abstract: A method for making a transistor with self-aligned gate and ground plane includes forming a stack, on one face of a semi-conductor substrate, the stack including an organometallic layer and a dielectric layer. The method also includes exposing a part of the organometallic layer, a portion of the organometallic layer different to the exposed part being protected from the electron beams by a mask, the shape and the dimensions of a section, in a plane parallel to the face of the substrate, of the gate of the transistor being substantially equal to the shape and to the dimensions of a section of the organometallic portion in said plane. The method also includes removing the exposed part, and forming dielectric portions in empty spaces formed by the removal of the exposed part of the organometallic layer, around the organometallic portion.

Abstract: A gate dielectric, an insulating layer and and an etching mask are formed on a substrate. The etching mask delineates at least the gate electrode and the source and drain contacts and the source, drain and gate output lines of the first metal level of a field effect device. The gate electrode and the future source and drain contacts are formed simultaneously by etching of the insulating layer. A gate material is deposited to form the gate electrode. The source and drain contacts are formed at least in the insulating layer. The source, drain and gate output lines of the first metal level are formed in the etching mask.

Abstract: A MOSFET on SOI device includes an upper region having at least one first MOSFET type semi-conductor device formed on a first semi-conductor layer stacked on a first dielectric layer, a first conductive layer and a first portion of a second semi-conductor layer. A lower region includes at least one second MOSFET type semi-conductor device formed on a second portion of the second semi-conductor layer, a gate of the second semi-conductor device being formed by at least one conductive portion. The second semi-conductor layer is arranged on a second dielectric layer stacked on a second conductive layer.

Abstract: A silicon substrate (SOI) is placed on a buried oxide layer (BOX). An MOS transistor is produced in an active zone of the substrate which is defined by an isolating region. A gate region and source and drain regions, which between them define a channel, are produced so that the gate region extends above the channel. The isolating region is produced by localized formation of a zone of material that can be selectively etched with respect to silicon. That material is selectively etched, and a dielectric material is deposited in the etched feature. The etching is carried out after the gate region has been produced. An upper surface of the substrate and an upper surface of the isolating region are flush with each other so as to define a planar surface on which the transistor gate region is formed.

Abstract: A silicon substrate (SOI) is placed on a buried oxide layer (BOX). An MOS transistor is produced in an active zone of the substrate which is defined by an isolating region. A gate region and source and drain regions, which between them define a channel, are produced so that the gate region extends above the channel. The isolating region is produced by localized formation of a zone of material that can be selectively etched with respect to silicon. That material is selectively etched, and a dielectric material is deposited in the etched feature. The etching is carried out after the gate region has been produced.

Abstract: An image sensor including photosensitive cells including photodiodes and at least one additional circuit with a significant heat dissipation including transistors. The image sensor is made in monolithic form and includes a layer of a semiconductor material having first and second opposite surfaces and including, on the first surface side, first regions corresponding to the power terminals of the transistors, the lighting of the image sensor being intended to be performed on the second surface side; a stack of insulating layers covering the first surface; a thermally conductive reinforcement covering the stack on the side opposite to the layer; and thermally conductive vias connecting the layer to the reinforcement.

Abstract: Transistor type semiconducting device comprising: a substrate, an insulating layer comprising sidewalls formed on each part of the source zone and the drain zone, drain, channel and source zones, the channel zone being formed on the insulating layer and being strained by the drain and the source zones, between the side parts, a grid, separated from the channel by a grid insulator.

Abstract: Method for making a transistor with self-aligned gate and ground plane, comprising the steps of: a) forming a stack, on one face of a semi-conductor substrate, comprising an organometallic layer and a dielectric layer, b) exposing a part of the organometallic layer, a portion of the organometallic layer different to the exposed part being protected from the electron beams by a mask, the shape and the dimensions of a section, in a plane parallel to the face of the substrate, of the gate of the transistor being substantially equal to the shape and to the dimensions of a section of said organometallic portion in said plane, c) removing the exposed part, d) forming dielectric portions in empty spaces formed by the removal of said exposed part of the organometallic layer, around said organometallic portion.

Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.

Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.

Abstract: MOSFET on SOI device, comprising: an upper region comprising at least one first MOSFET type semi-conductor device formed on a first semi-conductor layer stacked on a first dielectric layer, a first metallic layer and a first portion of a second semi-conductor layer, a lower region comprising at least one second MOSFET type semi-conductor device formed on a second portion of the second semi-conductor layer, a gate of the second semi-conductor device being formed by at least one metallic portion, the second semi-conductor layer being arranged on a second dielectric layer stacked on a second metallic layer.

Abstract: A single-crystal silicon region on insulator on silicon intended to receive at least one component, the insulator having overthicknesses.

Abstract: An image sensor including photosensitive cells including photodiodes and at least one additional circuit with a significant heat dissipation including transistors. The image sensor is made in monolithic form and includes a layer of a semiconductor material having first and second opposite surfaces and including, on the first surface side, first regions corresponding to the power terminals of the transistors, the lighting of the image sensor being intended to be performed on the second surface side; a stack of insulating layers covering the first surface; a thermally conductive reinforcement covering the stack on the side opposite to the layer; and thermally conductive vias connecting the layer to the reinforcement.

Abstract: A silicon substrate (SOI) is placed on a buried oxide layer (BOX). An MOS transistor is produced in an active zone of the substrate which is defined by an isolating region. A gate region and source and drain regions, which between them define a channel, are produced so that the gate region extends above the channel. The isolating region is produced by localized formation of a zone of material that can be selectively etched with respect to silicon. That material is selectively etched, and a dielectric material is deposited in the etched feature. The etching is carried out after the gate region has been produced.

Abstract: Transistor type semiconducting device comprising: a substrate, an insulating layer comprising sidewalls formed on each part of the source zone and the drain zone, drain, channel and source zones, the channel zone being formed on the insulating layer and being strained by the drain and the source zones, between the side parts, a grid, separated from the channel by a grid insulator.

Abstract: A single-crystal silicon region on insulator on silicon intended to receive at least one component, the insulator having overthicknesses.