Patents by Inventor Clement H. Wann
Clement H. Wann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8334570Abstract: A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film.Type: GrantFiled: March 4, 2011Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jeff J. Xu, Clement H. Wann, Chi Cheh Yeh, Chi-Sheng Chang
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Patent number: 8039331Abstract: An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.Type: GrantFiled: May 14, 2008Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Scott D. Allen, Cyril Cabral, Jr., Kevin K. Dezfulian, Sunfei Fang, Brian J. Greene, Rajarao Jammy, Christian Lavoie, Zhijiong Luo, Hung Ng, Chun-Yung Sung, Clement H. Wann, Huilong Zhu
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Publication number: 20110169085Abstract: A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film.Type: ApplicationFiled: March 4, 2011Publication date: July 14, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jeff J. Xu, Clement H. Wann, Chi Chieh Yeh, Chi-Sheng Chang
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Patent number: 7915112Abstract: A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film.Type: GrantFiled: September 23, 2008Date of Patent: March 29, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeff J. Xu, Clement H. Wann, Chi Chieh Yeh, Chi-Sheng Chang
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Patent number: 7791109Abstract: A local interconnect is formed with a gate conductor line that has an exposed sidewall on an active area of a semiconductor substrate. The exposes sidewall comprises a silicon containing material that may form a silicide alloy upon silicidation. During a silicidation process, a gate conductor sidewall silicide alloy forms on the exposed sidewall of the gate conductor line and an active area silicide is formed on the active area. The two silicides are joined to provide an electrical connection between the active area and the gate conductor line. Multiple sidewalls may be exposed on the gate conductor line to make multiple connections to different active area silicides.Type: GrantFiled: March 29, 2007Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Clement H. Wann, Haining S. Yang
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Patent number: 7785999Abstract: An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.Type: GrantFiled: July 30, 2007Date of Patent: August 31, 2010Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Chester T. Dziobkowski, Sunfei Fang, Evgeni Gousev, Rajarao Jammy, Vijay Narayanan, Vamsi Paruchuri, Ghavam G. Shahidi, Michelle L. Steen, Clement H. Wann
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Publication number: 20100072553Abstract: A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film.Type: ApplicationFiled: September 23, 2008Publication date: March 25, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jeff J. XU, Clement H. Wann, Chih Chieh Yeh, Chih-Sheng Chang
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Publication number: 20090256207Abstract: Disclosed herein is a transistor comprising a first fin having a first gate electrode disposed across the first fin; the gate electrode contacting opposing surfaces of the fin; and a planar oxide layer having a second gate electrode disposed across the planar oxide layer to form a planar metal oxide semiconductor field effect transistor; the first fin and the planar oxide layer being disposed upon a surface of a wafer.Type: ApplicationFiled: April 14, 2008Publication date: October 15, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiaomeng Chen, Bachir Dirahoui, William K. Henson, Michael D. Hulvey, Amit Kumar, Mahender Kumar, Amanda L. Tessier, Clement H. Wann
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Patent number: 7494915Abstract: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.Type: GrantFiled: August 9, 2006Date of Patent: February 24, 2009Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor, Erdem Kaltalioglu, Kaushik A. Kumar, Douglas C. La Tulipe, Jr., Jochen Schacht, Andrew H. Simon, Terry A. Spooner, Yun-Yu Wang, Clement H. Wann, Chih-Chao Yang
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Publication number: 20080239792Abstract: A local interconnect is formed with a gate conductor line that has an exposed sidewall on an active area of a semiconductor substrate. The exposes sidewall comprises a silicon containing material that may form a silicide alloy upon silicidation. During a silicidation process, a gate conductor sidewall silicide alloy forms on the exposed sidewall of the gate conductor line and an active area silicide is formed on the active area. The two silicides are joined to provide an electrical connection between the active area and the gate conductor line. Multiple sidewalls may be exposed on the gate conductor line to make multiple connections to different active area silicides.Type: ApplicationFiled: March 29, 2007Publication date: October 2, 2008Applicant: International Business Machines CorporationInventors: Clement H. Wann, Haining S. Yang
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Publication number: 20080220581Abstract: An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.Type: ApplicationFiled: May 14, 2008Publication date: September 11, 2008Applicant: International Business Machines CorporationInventors: Scott D. Allen, Cyril Cabral, Kevin K. Dezfulian, Sunfei Fang, Brian J. Greene, Rajarao Jammy, Christian Lavoie, Zhijiong Luo, Hung Ng, Chun-Yung Sung, Clement H. Wann, Huilong Zhu
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Patent number: 7410852Abstract: An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.Type: GrantFiled: April 21, 2006Date of Patent: August 12, 2008Assignee: International Business Machines CorporationInventors: Scott D. Allen, Cyril Cabral, Jr., Kevin K. Dezfulian, Sunfei Fang, Brian J. Greene, Rajarao Jammy, Christian Lavoie, Zhijiong Luo, Hung Ng, Chun-Yung Sung, Clement H. Wann, Huilong Zhu
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Patent number: 7282435Abstract: A method is provided of forming a contact to a semiconductor structure. A current-conducting member is formed which extends horizontally over a first portion of a semiconductor device region but not over a second portion of such semiconductor device region. A first film is formed which extends over the second portion and only partially over the member to expose a contact portion of the member. A first contact via is formed in conductive communication with the contact portion. The first contact via has a silicide-containing region self-aligned to an area of the member contacted by the contact via. A second contact via is formed in conductive communication with the second portion, the second contact via extending through the first film.Type: GrantFiled: July 25, 2006Date of Patent: October 16, 2007Assignee: International Business Machines CorporationInventors: Haining S. Yang, Clement H. Wann, Huilong Zhu
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Patent number: 7271455Abstract: An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.Type: GrantFiled: July 14, 2004Date of Patent: September 18, 2007Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Chester T. Dziobkowski, Sunfei Fang, Evgeni Gousev, Rajarao Jammy, Vijay Narayanan, Vamsi Paruchuri, Ghavam G. Shahidi, Michelle L. Steen, Clement H. Wann
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Patent number: 7122462Abstract: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.Type: GrantFiled: November 21, 2003Date of Patent: October 17, 2006Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor, Erdem Kaltalioglu, Kaushik A. Kumar, Douglas C. La Tulipe, Jr., Jochen Schacht, Andrew H. Simon, Terry A. Spooner, Yun-Yu Wang, Clement H. Wann, Chih-Chao Yang
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Patent number: 7122472Abstract: A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device having a first well region in a semiconductor substrate, first source/drain silicide areas in the first well region, and a first type gate isolated from the first source/drain silicide areas; forming a second type semiconductor device having a second well region in the semiconductor substrate, second source/drain silicide areas in the second well region, and a second type gate isolated from the second source/drain silicide areas; selectively forming a first metal layer over the second type semiconductor device; performing a first fully silicided (FUSI) gate formation on only the second type gate; depositing a second metal layer over the first and second type semiconductor devices; and performing a second FUSI gate formation on only the first type gate.Type: GrantFiled: December 2, 2004Date of Patent: October 17, 2006Assignee: International Business Machines CorporationInventors: Sunfei Fang, Cyril Cabral, Jr., Chester T. Dziobkowski, Christian Lavoie, Clement H. Wann
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Patent number: 7112481Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.Type: GrantFiled: October 20, 2005Date of Patent: September 26, 2006Assignee: International Business Machines CorporationInventors: Sunfei Fang, Cyril Cabral, Jr., Chester T. Dziobkowski, John J. Ellis-Monaghan, Christian Lavoie, Zhijiong Luo, James S. Nakos, An L. Steegen, Clement H. Wann
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Patent number: 7098536Abstract: A structure is provided which includes a semiconductor device region including a first portion and a second portion. A current-conducting member is provided, which extends horizontally over the first portion but not over the second portion. A first film, such as a stress-imparting film, extends over the second portion and only partially over the current-conducting member to expose a contact portion of the member. A first contact via is provided in conductive communication with the contact portion of the member, the first contact via having a self-aligned silicide-containing region. A second contact via is provided in conductive communication with the second portion of the semiconductor device region, the second contact via extending through the first film.Type: GrantFiled: October 21, 2004Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: Haining S. Yang, Clement H. Wann, Huilong Zhu
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Patent number: 7067368Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.Type: GrantFiled: October 20, 2005Date of Patent: June 27, 2006Assignee: International Business Machines CorporationInventors: Sunfei Fang, Cyril Cabral, Jr., Chester T. Dziobkowski, John J. Ellis-Monaghan, Christian Lavoie, Zhijiong Luo, James S. Nakos, An L. Steegen, Clement H. Wann
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Patent number: 7064025Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.Type: GrantFiled: December 2, 2004Date of Patent: June 20, 2006Assignee: International Business Machines CorporationInventors: Sunfei Fang, Cyril Cabral, Jr., Chester T. Dziobkowski, John J. Ellis-Monaghan, Christian Lavoie, Zhijiong Luo, James S. Nakos, An L. Steegen, Clement H. Wann