Abstract: The disclosure describes a method for transferring components for an electronic assembly. The process involves providing a wafer coupled to an energy activated release layer, and singulating the wafer into multiple components. A portion of the energy activated release layer is then activated, allowing for the removal of a component from the layer. Activation of the energy activated release layer occurs through a change in temperature, not with ultraviolet light. The components are removed without the use of a conventional ejector pin or needle and may be removed using a gang pickup. The change in temperature of the energy activated release layer may be heating or cooling. The change in temperature may be driven from above, below, or both above and below the energy activated release layer, including from a bottom thermal probe that may also act as a temperature changing ejector needle.

Abstract: An electronic assembly component may comprise at least one fan-out device comprising a first encapsulant disposed around a memory device or function and a processor device or function, and a fan-out interconnect structure disposed over the first encapsulant and the at least one fan-out device. Input output pads may be disposed over the fan-out interconnect structure. A structural support may comprise electrical routing and structural support pads, the structural support further comprising at least one mounting site to which the at least one fan-out device is coupled. An electrical connector may be configured to electrically couple the input output pads of the at least one fan-out device to the structural support pads. A second encapsulant may be disposed over at least a portion of the at least one fan-out device and the structural support.

Abstract: The disclosure concerns devices and methods of forming an electronic assembly or semiconductor assembly, such as fully molded structures, comprising at least two components of a same or differing heights, which may further comprise a backside conductive material. The backside conductive material may be a good thermal conductor, a good electrical conductor, or both.

Abstract: An electronic assembly component may comprise at least one fan-out device comprising a first encapsulant disposed around a memory device or function and a processor device or function, and a fan-out interconnect structure disposed over the first encapsulant and the at least one fan-out device. Input output pads may be disposed over the fan-out interconnect structure. A structural support may comprise electrical routing and structural support pads, the structural support further comprising at least one mounting site to which the at least one fan-out device is coupled. An electrical connector may be configured to electrically couple the input output pads of the at least one fan-out device to the structural support pads. A second encapsulant may be disposed over at least a portion of the at least one fan-out device and the structural support.

Abstract: An electronic assembly may include a component comprising conductive studs disposed over an active layer of the component. A first encapsulant layer may be disposed around four side surfaces of the component, over the active layer of the component, and contacting at least a portion of the sides of the conductive studs. A substantially planar surface may be disposed over the active layer of the component, wherein the substantially planar surface comprises ends of the conductive studs and the first encapsulant layer. The first encapsulant layer comprises a roughness less than 500 nanometers. First conductive elements may be disposed over the encapsulant and coupled with the conductive studs. A second layer of encapsulant may be disposed over the first conductive elements.

Abstract: An electrical or semiconductor package may comprise an embedded component comprising embedded vertical interconnects (EVIs) extending through a base substrate material from a first surface to a second surface opposite the first surface. An encapsulant may be disposed around and contact four side surfaces of the embedded component. A first electrical interconnect structure comprising a conductive stud may be coupled to a first end of the EVI at the first surface of the embedded component. The encapsulant may contact at least a portion of the side of the conductive stud. A second electrical interconnect structure comprising a portion of a conductive RDL layer may be coupled to a second end of the EVI at the second surface of the embedded component. A component may be coupled to, and mounted over, the first electrical interconnect of the vertical interconnect.

Abstract: A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.

Abstract: A method of making a semiconductor assembly may include providing a semiconductor component disposed within a first encapsulant, the encapsulant being disposed around and contacting at least four side surfaces of the semiconductor component and disposed over frontside of the semiconductor component. A first layered structure may be formed as a build-up interconnect structure over the encapsulant and over the semiconductor component. The first layered structure may comprise a first conductive layer formed over the first encapsulant, a first dielectric formed over the first conductive layer, and a second encapsulant disposed over first conductive layer and over first dielectric. An upper surface of the second encapsulant may be planarized to create a flat surface on which to form additional structures, such as a second layered structure or a package interconnect.

Abstract: A method and related structure for a encapsulant defined land grid array (LGA) may comprise a semiconductor chip comprising conductive studs disposed over an active layer of the semiconductor chip, and a first encapsulant disposed around at least a portion of sidewalls of the conductive studs. A surface of the first encapsulant and conductive studs may be planarized. Conductive traces may be disposed over the encapsulant and coupled with the conductive studs. A dielectric layer may be disposed adjacent the conductive traces. LGA pads may be coupled with the conductive traces. A second encapsulant may be disposed over the dielectric layer and the LGA pads. A planar surface may be formed comprising the second encapsulant around the LGA pads and attachment areas on or over the LGA pads. The plurality of attachment areas may be coplanar or recessed the planar surface.

Abstract: An electronic assembly may include a component comprising conductive studs disposed over an active layer of the component. A first encapsulant layer may be disposed around four side surfaces of the component, over the active layer of the component, and contacting at least a portion of the sides of the conductive studs. A substantially planar surface may be disposed over the active layer of the component, wherein the substantially planar surface comprises ends of the conductive studs and the first encapsulant layer. The first encapsulant layer comprises a roughness less than 500 nanometers. First conductive elements may be disposed over the encapsulant and coupled with the conductive studs. A second layer of encapsulant may be disposed over the first conductive elements.

Abstract: A method and related structure for a quad flat no-lead (QFN), dual flat no-lead (DFN) or small outline no-lead (SON) package without a leadframe. A semiconductor chip with conductive stumps over an active surface, a first layer of encapsulant disposed around the semiconductor chip, over the active surface, and around the conductive stumps, a first conductive layer and first vertical conductive contacts electrically coupled with the conductive stumps, the first conductive layer comprising conductive traces formed over a planarized surface of the encapsulant and conductive stumps, a second layer of encapsulant disposed over the first encapsulant layer, conductive layer, conductive traces, and first vertical conductive contacts, a plurality of conductive pads formed over a planarized surface, and a solderable metal system (SMS) formed or an organic solderability preservative (OSP) applied over at least a portion of the conductive pads.

Abstract: The disclosure concerns electronic assemblies, comprising: a component comprising conductive studs on a surface of the component; a first encapsulant disposed around four side surfaces of the component, over the surface of the component, and around at least a portion of sidewalls of the conductive studs; a conductive backside material disposed over at least a portion of a backside of the component; a substantially planar surface disposed over the surface of the component, wherein the substantially planar surface comprises ends of the conductive studs and a planar surface of the first encapsulant, wherein the planar surface of the first encapsulant comprises a roughness less than 500 nanometers over a characteristic measurement distance; conductive structures disposed over the planar surface and configured to be electrically coupled with the component; a second encapsulant disposed over the conductive structures; and conductive pads disposed over, or within, the second encapsulant for TO interconnection.

Abstract: An electronic assembly may include a component comprising conductive studs disposed over an active layer of the component. A first encapsulant layer may be disposed around four side surfaces of the component, over the active layer of the component, and contacting at least a portion of the sides of the conductive studs. A substantially planar surface may be disposed over the active layer of the component, wherein the substantially planar surface comprises ends of the conductive studs and the first encapsulant layer. The first encapsulant layer comprises a roughness less than 500 nanometers. First conductive elements may be disposed over the encapsulant and coupled with the conductive studs. A second layer of encapsulant may be disposed over the first conductive elements.

Abstract: An electronic assembly may include a component comprising conductive studs disposed over an active layer of the component. A first encapsulant layer may be disposed around four side surfaces of the component, over the active layer of the component, and contacting at least a portion of the sides of the conductive studs. A substantially planar surface may be disposed over the active layer of the component, wherein the substantially planar surface comprises ends of the conductive studs and the first encapsulant layer. The first encapsulant layer comprises a roughness less than 500 nanometers. First conductive elements may be disposed over the encapsulant and coupled with the conductive studs. A second layer of encapsulant may be disposed over the first conductive elements.

Abstract: A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.

Abstract: A method and related structure for a quad flat no-lead (QFN), dual flat no-lead (DFN) or small outline no-lead (SON) package without a leadframe. Disposing semiconductor chips face-up on a temporary carrier, disposing a first encapsulant layer around the semiconductor chip, the active layer and conductive stumps, forming a conductive layer and conductive contacts over the planar surface, disposing encapsulant over the first encapsulant layer, conductive layer and conductive contacts, forming a photoresist over the encapsulant with openings, forming conductive pads within the openings, forming a solderable metal system (SMS) or applying an organic solderability preservative (OSP) over the conductive pads, and cutting through the encapsulant around the chip to form the outline of a package.

Abstract: A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.

Abstract: A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.

Abstract: A multi-step conductive interconnect (MSI) may comprise a first step of the MSI comprising a first end and a second end opposite the first end, a first height (Ha) and a first diameter (Da). A second step of the MSI may comprise a first end and a second end opposite the first end. The first end of the second step contacts the second end of the first step. The second step may comprise a second height (Hb) and a second diameter (Db). The MSI may comprise a height (H) and a height to width aspect ratio (H:Da) greater than or equal to 1.5:1. A sidewall of the first step may comprise an offset (O) with respect to a sidewall of the second step to form a disjointed sidewall profile. The offset O may be in a range of 0.1 ?m-20 ?m.

Abstract: A semiconductor device may comprise a bridge die comprising copper studs. Copper posts may be disposed in a periphery of the bridge die. An encapsulant may be disposed on five sides of the bridge die, on sides of the copper studs, and on sides of the copper posts that leave ends of the copper studs and opposing first and second ends of the copper posts exposed from the encapsulant. A frontside build-up interconnect structure may be formed over the copper studs of the bridge die and coupled to second ends of the copper posts opposite the first ends of the copper posts. The frontside build-up interconnect structure comprising first pads at a first pitch within a footprint of the bridge die and second pads at a second pitch outside a footprint of the bridge die. The first pitch may be at least 1.5 times less than the second pitch.