Abstract: A method for calibrating (700) an antenna array comprises a plurality of antenna elements coupled to a plurality of respective receive paths in a wireless communication system. The method comprises, in receive mode, applying a test signal to an individual single receive path (715) of the plurality of receive paths; and feeding back the test signal via a switched coupler network. The method further comprises running a receive calibration measurement routine to determine at least one measurement value used to calibrate the individual signal receive path and waiting for at least one converged measurement value; and extracting (720) the converged measurement value for at least one individual receive path. The steps of applying, running, extracting for a next individual single receive path are repeated until the calibration routine has completed (725).

Abstract: An apparatus comprises a number of sub-systems and a control interface operably coupled to sub-systems for routing data therebetween. A strobe generation function is operably coupled to the control interface and configured to generate a plurality of different strobe signals to differentiate between different intended receiving devices. Thus, different strobe signals may be multiplexed onto a single control interface link, based on a pulse width or voltage magnitude characteristics of the respective strobe signals. A strobe decoder function is operably coupled to the control interface and configured to decode a plurality of different strobe signals to differentiate between triggering sub-systems on receiving devices.

Abstract: A network element for a wireless communication system is locatable to couple at least one base station to an antenna array comprising a plurality of antenna elements. The network element comprises a plurality of independent transceiver circuits coupled to at least one of a plurality of respective antenna elements of the antenna array; and logic arranged to apply at least one complex digital signal to at least one transceiver signal path of a transceiver circuit of the plurality of independent transceiver circuits. A feedback path is arranged to provide feedback of the at least one complex digital signal such that it is capable of facilitating determination of latency mismatch error response between at least two transceiver signal paths. Adjustment means comprises delay logic arranged to receive a complex digital signal and provide a modified representation of the received complex digital signal in response to the latency mismatch error response of the at least two transceiver signal path.

Abstract: A calibration signal generator for use in a balancing circuit calibration device in a radio receiver, the calibration signal generator comprising: a means of amplifying a clocking signal from a clocking signal generator to provide a first calibration signal; a means of generating a second calibration signal from the clocking signal, the first and second calibration signals being transmissible to a one or more mixing circuits in the balancing circuit calibration device; and a means synchronizing the operation of other circuit elements in the balancing circuit calibration device with the clocking signal; characterized in that the clocking signal generator is present in the radio receiver and used therein for other functions.

Abstract: An integrated circuit comprising processing logic for operably coupling to radio frequency (RF) receiver circuitry arranged to receive a wireless network signal. The receiver circuitry generates in-phase and quadrature digital baseband representations of the wireless network signal. The processing logic determines quadrature (I/Q) imbalance of the RF receiver circuitry based on the in-phase and quadrature digital baseband representations of the wireless network signal.

Abstract: A semiconductor device comprises sampling logic, comprising: input sample path selection logic arranged to enable at least one input sample path; sampler logic arranged to receive and sample an input data signal in a serial data stream in accordance with a phase of the at least one enabled input sample path; and transition detection logic arranged to detect transitions within the received input data signal. The input sample path selection logic is further arranged, upon detection of a transition within the received input data signal, to determine if the phase of the at least one input sample path is a phase having a largest window between logic values; and if it is determined that the phase of the at least one input sample path is not the phase having a largest window between logic values, to enable at least one input sample path comprising a more appropriate phase.

Abstract: A method for processing at least one polarization type of at least one wireless signal by a communication unit operably couplable to an antenna arrangement that comprises at least two orthogonally polarized antenna elements. The method comprises processing at least one signal radiated by at least one first antenna element of the antenna arrangement; and processing the at least one signal where processing comprises at least applying at least one digital complex scaling operation on the at least one signal radiated by at least one second antenna element of orthogonal polarization to the at least one first antenna element of the antenna arrangement thereby radiating at least one wireless signal of at least one non-native polarization type.

Abstract: A semiconductor device comprising interface logic for transmitting data bursts across an interface. The interface logic is arranged to transmit bursts of data across the interface such that the start of a burst of data is substantially aligned with a symbol interval (SI) boundary. The interface logic is further arranged to apply an offset to the SI boundary at the start of the burst of data.

Abstract: A semiconductor device comprising an interface logic module for transmitting data frames across an interface, and controller logic module arranged to control a rate at which the interface logic transmits data across the interface. Upon receipt of data frames to transmit across the interface, the controller logic module is arranged to determine a sequence of data rates with which to transmit sequential data frames across the interface, and to configure the transmission of the data frames across the interface according to the determined data rate sequence. The selection of these data rates will be dependent on specific critical RF frequencies where EMI impacts have to be minimized.

Abstract: A very low intermediate frequency (VLIF) receiver comprising a first and second mixer circuits, characterised in that receiver comprises a means of estimating the energy in a desired signal band; a means of estimating the energy in a band of frequencies comprising the desired signal band; and a means of altering a VLIF of the receiver according to the ratio of the energy in a desired signal band and the energy in the band of frequencies comprising the desired signal band.

Abstract: A semiconductor device comprising interface logic for transmitting data bursts across an interface. The interface logic is arranged to transmit bursts of data across the interface such that the start of a burst of data is substantially aligned with a symbol interval (SI) boundary. The interface logic is further arranged to apply an offset to the SI boundary at the start of the burst of data.

Abstract: A network element for a wireless communication system is locatable to couple at least one base station to an antenna array. The network element comprises at least one receiver arranged to receive a radio frequency signal from the at least one base station or the antenna array and modem logic operably coupled to the at least one receiver. The modem logic comprises radio frequency conversion circuitry arranged to down-convert a received radio frequency signal to a baseband signal; analogue-to-digital conversion logic arranged to convert the baseband signal to digitized signals; and beam-form processing logic arranged to perform active beam-forming adjustment on the digitized signals.

Abstract: Receiver circuitry for processing a received Very Low Intermediate Frequency signal wherein the receiver circuitry comprises a main processing path. The main processing path comprises mixing circuitry arranged to mix a received VLIF signal with a frequency down conversion signal to produce a main path signal. The receiver circuitry further comprises a direct current cancellation path comprising mixing circuitry arranged to mix a DC element of the received VLIF signal with the frequency down conversion signal to produce a DC cancellation signal. The receiver circuitry still further comprises signal summing circuitry arranged to add the DC cancellation signal in anti-phase with the main path signal.

Abstract: A wireless communication unit comprises a transmitter having a power amplifier and a feedback path operably coupled to the power amplifier. The feedback path comprises a coupler for feeding back a portion of a signal to be transmitted and a detector for detecting a power level of the fed back signal. A controller provides a ramp signal to the power amplifier that controls an amplitude characteristic of the signal to be transmitted. Averaging logic is operably coupled to the detector and arranged to average the detected power level over a first period. Comparison logic is operably coupled to the averaging logic and arranged to compare the average detected power level with a reference value. The controller is operably coupled to the comparison logic and arranged to scale a ramp signal applied to the power amplifier in response to the comparison.

Abstract: An electronic device comprises a number of sub-systems coupled via an interface. One of the number of sub-systems comprises logic for receiving a frame of input data having a plurality of phases on respective data paths. The electronic device further comprises logic for performing cross correlation on the received input data with a pre-determined bit pattern, operably coupled to selection logic, for selecting a single phase from the plurality of phases sent to the interface to sample the received input data in a middle region of a data bit period in response to the cross correlation.

Abstract: A wireless communication unit includes a baseband module and a radiofrequency module. A communication interface connects the baseband module to the radiofrequency module. Data can be communicated from the baseband module to the radiofrequency module and/or vice versa via the interface. The communication interface includes one or more data compression arrangement, for compressing original data to be transmitted over the communication interface, from a transmitting side of the communication interface to a receiving side of the communication interface, into compressed data and decompressing the compressed data after transmission and restoring the original data. The data compression arrangement may include a data compression unit at the transmitting side of the communication interface, and a data decompression unit at the receiving side of the communication interface.

Abstract: A master radiofrequency integrated circuit (RF IC) and a slave radiofrequency integrated circuit include a master radiofrequency module and a slave radiofrequency module, respectively. Both RF ICs include a radiofrequency side contact connectable to an antenna, for receiving radiofrequency signals, via the antenna, from a wireless communications network and a baseband side contact connected to the radiofrequency module and connectable to a contact of a baseband integrated circuit, for transmitting the baseband signals from the master radiofrequency module to the baseband integrated circuit. The RF module is connected to the radiofrequency side contact, for converting the radiofrequency signals into baseband signals. The master radiofrequency module includes a slave control unit for controlling the slave radiofrequency module.

Abstract: A method for processing at least one polarization type of at least one wireless signal by a communication unit operably couplable to an antenna arrangement that comprises at least two orthogonally polarized antenna elements. The method comprises processing at least one signal radiated by at least one first antenna element of the antenna arrangement; and processing the at least one signal where processing comprises at least applying at least one digital complex scaling operation on the at least one signal radiated by at least one second antenna element of orthogonal polarization to the at least one first antenna element of the antenna arrangement thereby radiating at least one wireless signal of at least one non-native polarization type.

Abstract: A method of processing location information on a mobile device which includes a primary receiver for receiving a primary signal; a diversity receiver for receiving a diversity signal or location information; a diversity combiner which can combine primary and diversity signals to form a combined signal; and a first processing unit for processing the combined signal; the method comprising the steps of: identifying whether the device is in a location mode or a diversity mode; if the device is in location mode, disabling the diversity combiner; passing the output from the primary receiver directly to the first processing unit; and passing location information from the diversity receiver to a location processing unit.

Abstract: A wireless communication device comprises a number of sub-systems and clock generation logic arranged to generate at least one clock signal to be applied to the number of sub-systems. One of the number of sub-systems comprises sampling logic for receiving input data and performing initial sampling on an input data bit using multiple separated phases of a clock period of the at least one clock signal applied to the sampling logic thereby producing multiple phase separated sampled outputs of the input data bit. The sampling logic is configured to perform a number of re-sampling operations on the multiple phase separated sampled outputs at a number of intermediate phases thereby producing multiple phase separated intermediate sampled outputs prior to performing a final sample of the multiple phase separated intermediate sampled outputs at a single phase of the at least one clock signal to produce a sampled input data signal.