Abstract: A wireless communication device comprises a number of sub-systems operably coupled to a data interface for routeing data between the number of sub-systems. A clock generation function generates a clock signal substantially at a data transfer rate to be used over the data interface whereby the clock signal is generated at a rate that minimises harmonic content of the clock signal at operational frequencies of the wireless communication device. Thus, a suitable data rate is selected and supported by the data interface that accommodates the desired bandwidth, clock rate and/or chip rate of the functional elements that are coupled by the data interface within the wireless communication device, whilst minimising the effects of harmonic interference from the clock signal(s).

Abstract: A method of processing location information on a mobile device which includes a primary receiver for receiving a primary signal; a diversity receiver for receiving a diversity signal or location information; a diversity combiner which can combine primary and diversity signals to form a combined signal; and a first processing unit for processing the combined signal; the method comprising the steps of: identifying whether the device is in a location mode or a diversity mode; if the device is in location mode, disabling the diversity combiner; passing the output from the primary receiver directly to the first processing unit; and passing location information from the diversity receiver to a location processing unit.

Abstract: A wireless communication device comprises a number of sub-systems and clock generation logic arranged to generate at least one clock signal to be applied to the number of sub-systems. One of the number of sub-systems comprises sampling logic for receiving input data and performing initial sampling on an input data bit using multiple separated phases of a clock period of the at least one clock signal applied to the sampling logic thereby producing multiple phase separated sampled outputs of the input data bit. The sampling logic is configured to perform a number of re-sampling operations on the multiple phase separated sampled outputs at a number of intermediate phases thereby producing multiple phase separated intermediate sampled outputs prior to performing a final sample of the multiple phase separated intermediate sampled outputs at a single phase of the at least one clock signal to produce a sampled input data signal.

Abstract: A communications device comprises a receiver for receiving an input signal operably coupled to analogue to digital converter logic. The analogue to digital converter logic is operably coupled to control logic via a signal analyser arranged to analyse a converted received input signal, output from the analogue to digital converter logic to determine at least one characteristic of the received signal. The control logic is arranged to vary a dynamic range of the analogue to digital converter logic depending on the at least one determined characteristic of the received input signal.

Abstract: An apparatus comprises a number of sub-systems and a control interface operably coupled to sub-systems for routeing data therebetween. A strobe generation function is operably coupled to the control interface and configured to generate a plurality of different strobe signals to differentiate between different intended receiving devices. Thus, different strobe signals may be multiplexed onto a single control interface link, based on a pulse width or voltage magnitude characteristics of the respective strobe signals. A strobe decoder function is operably coupled to the control interface and configured to decode a plurality of different strobe signals to differentiate between triggering sub-systems on receiving devices.

Abstract: A high pass filter adapted for use in a signal processing device comprising a sampler adapted to sample a signal and transmit the samples to the high pass filter, the high pass filter comprising a differentiator and an integrator; a counter which, in use, counts the number of samples received by the high pass filter from the sampler; and a control device which receives a first signal from the counter when the high pass filter has received a first sample from the sampler and receives a second signal from the counter when the high pass filter has received a second or subsequent sample from the sampler; whereupon receipt of the first signal, the control device causes the integrator output signal to substantially equal zero and whereupon receipt of the second signal, the control device causes the integrator output to be a function of an input signal from the differentiator.

Abstract: A wireless communication device comprises a number of sub-systems operably coupled to a data interface for routing data between the number of sub-systems. A clock generation function generates a clock signal substantially at a data transfer rate to be used over the data interface whereby the clock signal is generated at a rate that minimises harmonic content of the clock signal at operational frequencies of the wireless communication device. Thus, a suitable data rate is selected and supported by the data interface that accommodates the desired bandwidth, clock rate and/or chip rate of the functional elements that are coupled by the data interface within the wireless communication device, whilst minimising the effects of harmonic interference from the clock signal(s).