Patents by Inventor Cornelia K. Tsang
Cornelia K. Tsang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9355936Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.Type: GrantFiled: April 1, 2014Date of Patent: May 31, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Edward C. Cooney, III, James S. Dunn, Dale W. Martin, Charles S. Musante, BethAnn Rainey Lawrence, Leathen Shi, Edmund J. Sprogis, Cornelia K. Tsang
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Publication number: 20160133498Abstract: A method for adhesive bonding in microelectronic device processing is provided that includes bonding a handling wafer to a front side of a device wafer with an adhesive comprising phenoxy resin; and thinning the device wafer from the backside of the device wafer while the device wafer is adhesively engaged to the handling wafer. After the device wafer has been thinned, the adhesive comprising phenoxy resin may be removed by laser debonding, wherein the device wafer is separated from the handling wafer.Type: ApplicationFiled: November 7, 2014Publication date: May 12, 2016Inventors: Robert D. Allen, Paul S. Andry, Jeffrey D. Gelorme, Li-wen Hung, John U. Knickerbocker, Cornelia K. Tsang
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Publication number: 20160133501Abstract: A method for adhesive bonding in microelectronic device processing is provided that includes bonding a handling wafer to a front side of a device wafer with an adhesive comprising phenoxy resin; and thinning the device wafer from the backside of the device wafer while the device wafer is adhesively engaged to the handling wafer. After the device wafer has been thinned, the adhesive comprising phenoxy resin may be removed by laser debonding, wherein the device wafer is separated from the handling wafer.Type: ApplicationFiled: November 17, 2015Publication date: May 12, 2016Inventors: Robert D. Allen, Paul S. Andry, Jeffrey D. Gelorme, Li-wen Hung, John U. Knickerbocker, Cornelia K. Tsang
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Patent number: 9331141Abstract: CMOS structures with a replacement substrate and methods of manufacture are disclosed herein. The method includes forming a device on a temporary substrate. The method further includes removing the temporary substrate. The method further includes bonding a permanent electrically insulative substrate to the device with a bonding structure.Type: GrantFiled: February 21, 2013Date of Patent: May 3, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Paul S. Andry, Edmund J. Sprogis, Cornelia K. Tsang
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Patent number: 9324601Abstract: A method for adhesive bonding in microelectronic device processing is provided that includes bonding a handling wafer to a front side of a device wafer with an adhesive comprising phenoxy resin; and thinning the device wafer from the backside of the device wafer while the device wafer is adhesively engaged to the handling wafer. After the device wafer has been thinned, the adhesive comprising phenoxy resin may be removed by laser debonding, wherein the device wafer is separated from the handling wafer.Type: GrantFiled: November 7, 2014Date of Patent: April 26, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert D. Allen, Paul S. Andry, Jeffrey D. Gelorme, Li-wen Hung, John U. Knickerbocker, Cornelia K. Tsang
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Patent number: 9313921Abstract: A package structure to implement two-phase cooling includes a chip stack disposed on a substrate, and a package lid that encloses the chip stack. The chip stack includes a plurality of conjoined chips, a central inlet manifold formed through a central region of the chip stack, and a peripheral outlet manifold. The central input manifold includes inlet nozzles to feed liquid coolant into flow cavities formed between adjacent conjoined chips. The peripheral outlet manifold outputs heated liquid and vapor from the flow cavities. The package lid includes a central coolant supply inlet aligned to the central inlet manifold, and a peripheral liquid-vapor outlet to output heated liquid and vapor that exits from the peripheral outlet manifold. Guiding walls may be included in the flow cavities to guide a flow of liquid and vapor, and the guiding walls can be arranged to form radial flow channels that are feed by different inlet nozzles of the central inlet manifold.Type: GrantFiled: August 30, 2013Date of Patent: April 12, 2016Assignee: International Business Machines CorporationInventors: Thomas J. Brunschwiler, Evan G. Colgan, John U. Knickerbocker, Bruno Michael, Chin Lee Ong, Cornelia K. Tsang
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Publication number: 20150357283Abstract: A method of forming an integrated circuit assembly includes forming an insulator layer on a preliminary semiconductor assembly. The preliminary semiconductor assembly includes a semiconductor substrate having a first side and a second side opposite the first side, a semiconductor circuitry layer formed on the first side of the semiconductor substrate, and a conductive via extending through the semiconductor substrate from the semiconductor circuitry layer to the second side. The insulator is formed on the second side and an end of the conductive via. The method includes forming a polymer layer on the insulator layer, removing a quantity of the polymer layer sufficient to expose the end of the conductive via through the insulator layer, and forming a conductive contact on the polymer layer and the end of the conductive via.Type: ApplicationFiled: August 18, 2015Publication date: December 10, 2015Inventors: Paul S. Andry, Sarah H. Knickerbocker, Ron R. Legario, Cornelia K. Tsang, Melvin P. Zussman
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Patent number: 9209128Abstract: A method of forming an integrated circuit assembly includes forming an insulator layer on a preliminary semiconductor assembly. The preliminary semiconductor assembly includes a semiconductor substrate having a first side and a second side opposite the first side, a semiconductor circuitry layer formed on the first side of the semiconductor substrate, and a conductive via extending through the semiconductor substrate from the semiconductor circuitry layer to the second side. The insulator is formed on the second side and an end of the conductive via. The method includes forming a polymer layer on the insulator layer, removing a quantity of the polymer layer sufficient to expose the end of the conductive via through the insulator layer, and forming a conductive contact on the polymer layer and the end of the conductive via.Type: GrantFiled: April 1, 2014Date of Patent: December 8, 2015Assignees: International Business Machines Corporation, HITACHI CHEMICAL DUPONT MICROSYSTEMS, L.L.C.Inventors: Paul S. Andry, Sarah H. Knickerbocker, Ron R. Legario, Cornelia K. Tsang, Melvin P. Zussman
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Patent number: 9171749Abstract: A method of removing a handler wafer. There is provided a handler wafer and a semiconductor device wafer having a plurality of semiconductor devices, the semiconductor device wafer having an active surface side and an inactive surface side. An amorphous carbon layer is applied to a surface of the handler wafer. An adhesive layer is applied to at least one of the amorphous carbon layer of the handler wafer and the active surface side of the semiconductor device wafer. The handler wafer is joined to the semiconductor device wafer through the adhesive layer or layers. Laser radiation is applied to the handler wafer to cause heating of the amorphous carbon layer that in turn causes heating of the adhesive layer or layers. The plurality of semiconductor devices of the semiconductor device wafer are then separated from the handler wafer.Type: GrantFiled: November 13, 2013Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES U.S.2 LLCInventors: Bing Dang, Sarah H. Knickerbocker, Douglas C. La Tulipe, Jr., Spyridon Skordas, Cornelia K. Tsang, Kevin R. Winstel
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Patent number: 9159602Abstract: Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.Type: GrantFiled: August 19, 2009Date of Patent: October 13, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul S. Andry, John M. Cotte, John U. Knickerbocker, Cornelia K. Tsang
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Publication number: 20150287960Abstract: A system comprising a first dielectric element and a second dielectric element each having a first surface, wherein the first surface of the first dielectric element and the first surface of the second dielectric element are joined. The system further comprises one or more enclosed voids within the joined first and second dielectric elements. The system further comprises a flexible battery in a first enclosed void of the one or more enclosed voids, the flexible battery having a thickness of less than about 150 microns.Type: ApplicationFiled: July 24, 2014Publication date: October 8, 2015Inventors: Paul S. Andry, Joana Sofia Branquinho Teresa Maria, Bing Dang, Michael A. Gaynes, John U. Knickerbocker, Eric P. Lewandowski, Cornelia K. Tsang, Bucknell C. Webb
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Publication number: 20150279779Abstract: A method of forming an integrated circuit assembly includes forming an insulator layer on a preliminary semiconductor assembly. The preliminary semiconductor assembly includes a semiconductor substrate having a first side and a second side opposite the first side, a semiconductor circuitry layer formed on the first side of the semiconductor substrate, and a conductive via extending through the semiconductor substrate from the semiconductor circuitry layer to the second side. The insulator is formed on the second side and an end of the conductive via. The method includes forming a polymer layer on the insulator layer, removing a quantity of the polymer layer sufficient to expose the end of the conductive via through the insulator layer, and forming a conductive contact on the polymer layer and the end of the conductive via.Type: ApplicationFiled: April 1, 2014Publication date: October 1, 2015Applicants: Hitachi Chemical DuPont Microsystems, L.L.C., International Business Machines CorporationInventors: Paul S. Andry, Sarah H. Knickerbocker, Ron R. Legario, Cornelia K. Tsang, Melvin P. Zussman
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Publication number: 20150221613Abstract: An electrical device that includes at least two active wafers having at least one through silicon via, and at least one unitary electrical communication and spacer structure present between a set of adjacently stacked active wafers of the at least two active wafers. The unitary electrical communication and spacer structure including an electrically conductive material core providing electrical communication to the at least one through silicon via structure in the set of adjacently stacked active wafers and a substrate material outer layer. The at least one unitary electrical communication and spacer structure being separate from and engaged to the adjacently stacked active wafers, wherein coolant passages are defined between surfaces of the adjacently stacked active wafers and the at least one unitary electrical communication and spacer structure.Type: ApplicationFiled: January 30, 2015Publication date: August 6, 2015Inventors: Paul S. Andry, Mark D. Schultz, Cornelia K. Tsang
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Publication number: 20150132924Abstract: A method of removing a handler wafer. There is provided a handler wafer and a semiconductor device wafer having a plurality of semiconductor devices, the semiconductor device wafer having an active surface side and an inactive surface side. An amorphous carbon layer is applied to a surface of the handler wafer. An adhesive layer is applied to at least one of the amorphous carbon layer of the handler wafer and the active surface side of the semiconductor device wafer. The handler wafer is joined to the semiconductor device wafer through the adhesive layer or layers. Laser radiation is applied to the handler wafer to cause heating of the amorphous carbon layer that in turn causes heating of the adhesive layer or layers. The plurality of semiconductor devices of the semiconductor device wafer are then separated from the handler wafer.Type: ApplicationFiled: November 13, 2013Publication date: May 14, 2015Applicant: International Business Machines CorporationInventors: Bing Dang, Sarah H. Knickerbocker, Douglas C. La Tulipe, JR., Spyridon Skordas, Cornelia K. Tsang, Kevin R. Winstel
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Patent number: 8927087Abstract: Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One structure includes: a first substrate having a metal-dielectric pattern on a surface thereof, the metal-dielectric pattern including: a metal having a concave upper surface; and a dielectric having a substantially uniform upper surface, wherein the metal on the first substrate is raised above the dielectric on the first substrate; and a second substrate bonded with the first substrate, the second substrate including: a dielectric; and a metal positioned substantially below the dielectric of the second substrate, wherein the first substrate and the second substrate are bonded only at the metal from the first substrate and the metal from the second substrate.Type: GrantFiled: September 17, 2013Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Kuan-Neng Chen, Bruce K. Furman, Sampath Purushothaman, David L. Rath, Anna W. Topol, Cornelia K. Tsang
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Publication number: 20140209908Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.Type: ApplicationFiled: April 1, 2014Publication date: July 31, 2014Applicant: International Business Machines CorporationInventors: Edward C. Cooney, III, James S. Dunn, Dale W. Martin, Charles S. Musante, BethAnn Rainey Lawrence, Leathen Shi, Edmund J. Sprogis, Cornelia K. Tsang
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Patent number: 8778737Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.Type: GrantFiled: October 31, 2011Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, James S. Dunn, Dale W. Martin, Charles F. Musante, BethAnn Rainey, Leathen Shi, Edmund J. Sprogis, Cornelia K. Tsang
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Publication number: 20140097543Abstract: Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One structure includes: a first substrate having a metal-dielectric pattern on a surface thereof, the metal-dielectric pattern including: a metal having a concave upper surface; and a dielectric having a substantially uniform upper surface, wherein the metal on the first substrate is raised above the dielectric on the first substrate; and a second substrate bonded with the first substrate, the second substrate including: a dielectric; and a metal positioned substantially below the dielectric of the second substrate, wherein the first substrate and the second substrate are bonded only at the metal from the first substrate and the metal from the second substrate.Type: ApplicationFiled: September 17, 2013Publication date: April 10, 2014Applicant: International Business Machines CorporationInventors: Kuan-Neng Chen, Bruce K. Furman, Sampath Purushothaman, David L. Rath, Anna W. Topol, Cornelia K. Tsang
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Patent number: 8679280Abstract: A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC), includes attaching the handler to the wafer using an adhesive comprising a thermoset polymer, the handler comprising a material that is transparent in a wavelength range of about 193 nanometers (nm) to about 400 nm; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer.Type: GrantFiled: May 27, 2010Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: Bing Dang, Matthew Farinelli, John Knickerbocker, Aparna Prabhakar, Robert E. Trzcinski, Cornelia K. Tsang
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Publication number: 20140071628Abstract: A package structure to implement two-phase cooling includes a chip stack disposed on a substrate, and a package lid that encloses the chip stack. The chip stack includes a plurality of conjoined chips, a central inlet manifold formed through a central region of the chip stack, and a peripheral outlet manifold. The central input manifold includes inlet nozzles to feed liquid coolant into flow cavities formed between adjacent conjoined chips. The peripheral outlet manifold outputs heated liquid and vapor from the flow cavities. The package lid includes a central coolant supply inlet aligned to the central inlet manifold, and a peripheral liquid-vapor outlet to output heated liquid and vapor that exits from the peripheral outlet manifold. Guiding walls may be included in the flow cavities to guide a flow of liquid and vapor, and the guiding walls can be arranged to form radial flow channels that are feed by different inlet nozzles of the central inlet manifold.Type: ApplicationFiled: August 30, 2013Publication date: March 13, 2014Inventors: Thomas J. Brunschwiler, Evan G. Colgan, John U. Knickerbocker, Bruno Michael, Chin Lee Ong, Cornelia K. Tsang