Patents by Inventor Cornelius Christian Russ

Cornelius Christian Russ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9859270
    Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: January 2, 2018
    Assignee: Infineon Technologies AG
    Inventors: Cornelius Christian Russ, David Alvarez
  • Patent number: 9728512
    Abstract: Electrostatic discharge clamp devices are described. In one embodiment, the semiconductor device includes a first transistor, the first transistor including a first source/drain and a second source/drain, the first source/drain coupled to a first potential node, the second source/drain coupled to a second potential node. The device further includes a OR logic block, a first input of the OR logic block coupled to the first potential node through a capacitor, the first input of the OR logic block being coupled to the second potential node through a resistor, and a second input of the OR logic block coupled to a substrate pickup node of the first transistor.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: August 8, 2017
    Assignee: Infineon Technologies AG
    Inventor: Cornelius Christian Russ
  • Patent number: 9647069
    Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: May 9, 2017
    Assignee: Infineon Technologies AG
    Inventors: Mayank Shrivastava, Cornelius Christian Russ, Harald Gossner, Ramgopal Rao
  • Patent number: 9478979
    Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: October 25, 2016
    Assignee: Infineon Technologies AG
    Inventors: Krzysztof Domanski, Wolfgang Soldner, Cornelius Christian Russ, David Alvarez, Adrien Ille
  • Patent number: 9455275
    Abstract: In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: September 27, 2016
    Assignee: Infineon Techologies AG
    Inventors: Mayank Shrivastava, Maryam Shojaei Baghini, Cornelius Christian Russ, Harald Gossner, Ramgopal Rao
  • Publication number: 20160071833
    Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.
    Type: Application
    Filed: November 16, 2015
    Publication date: March 10, 2016
    Inventors: Cornelius Christian Russ, David Alvarez
  • Patent number: 9263428
    Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: February 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Cornelius Christian Russ, David Alvarez
  • Patent number: 9263430
    Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: February 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Krzysztof Domanski, Cornelius Christian Russ, Kai Esmark
  • Publication number: 20150357322
    Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.
    Type: Application
    Filed: August 20, 2015
    Publication date: December 10, 2015
    Inventors: Cornelius Christian Russ, David Alvarez
  • Publication number: 20150340442
    Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.
    Type: Application
    Filed: June 18, 2015
    Publication date: November 26, 2015
    Inventors: Mayank Shrivastava, Cornelius Christian Russ, Harald Gossner, Ramgopal Rao
  • Patent number: 9129805
    Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: September 8, 2015
    Assignee: Infineon Technologies AG
    Inventors: Cornelius Christian Russ, David Alvarez
  • Publication number: 20150229126
    Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.
    Type: Application
    Filed: April 20, 2015
    Publication date: August 13, 2015
    Inventors: Krzysztof Domanski, Wolfgang Soldner, Cornelius Christian Russ, David Alvarez, Adrien Ille
  • Patent number: 9087892
    Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: July 21, 2015
    Assignee: Infineon Technologies AG
    Inventors: Mayank Shrivastava, Cornelius Christian Russ, Harald Gossner, Ramgopal Rao
  • Publication number: 20150144996
    Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.
    Type: Application
    Filed: January 27, 2015
    Publication date: May 28, 2015
    Inventors: Krzysztof Domanski, Cornelius Christian Russ, Kai Esmark
  • Patent number: 9013842
    Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: April 21, 2015
    Assignee: Infineon Technologies AG
    Inventors: Krzysztof Domanski, Wolfgang Soldner, Cornelius Christian Russ, David Alvarez, Adrien Ille
  • Publication number: 20140145265
    Abstract: In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.
    Type: Application
    Filed: January 30, 2014
    Publication date: May 29, 2014
    Inventors: Mayank Shrivastava, Maryam Shojaei Baghini, Cornelius Christian Russ, Harald Gossner, Ramgopal Rao
  • Patent number: 8664720
    Abstract: In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: March 4, 2014
    Assignee: Infineon Technologies AG
    Inventors: Mayank Shrivastava, Maryam Shojaei Baghini, Cornelius Christian Russ, Harald Gossner, Ramgopal Rao
  • Publication number: 20140015010
    Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.
    Type: Application
    Filed: September 16, 2013
    Publication date: January 16, 2014
    Inventors: Mayank Shrivastava, Cornelius Christian Russ, Harald Gossner, Ramgopal Rao
  • Publication number: 20130264645
    Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.
    Type: Application
    Filed: June 4, 2013
    Publication date: October 10, 2013
    Inventors: Cornelius Christian Russ, David Alvarez
  • Publication number: 20130264646
    Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.
    Type: Application
    Filed: June 4, 2013
    Publication date: October 10, 2013
    Inventors: Cornelius Christian Russ, David Alvarez