Patents by Inventor Costantino Pala
Costantino Pala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11483005Abstract: Described herein are a method and apparatus for a selective SYSREF (SYStem REFerence signal) scheme that is driven by an external SYSREF source for a system that may include, for example, analog blocks, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), radio frequency (RF) arrays, as well as digital blocks, which may include JESD serializer/deserializer (SERDES) Transport and Link Layer circuitry, all of which can be operating at different clock frequencies. In one aspect, synchronization of the components is achieved when an internal SYSREF for the analog blocks is keyed off the external SYSREF, but the internal SYSREF pulse used by the digital blocks is programmatically keyed off one of the periodic internal SYSREF pulses. Additionally, a mechanism is provided for synchronization of the programmatically selected internal SYSREF across different clock domains in the digital blocks.Type: GrantFiled: June 28, 2022Date of Patent: October 25, 2022Assignee: IQ-Analog, Inc.Inventors: Gregory Uvieghara, Kenneth Pettit, Costantino Pala, Mikko Waltari
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Patent number: 10498350Abstract: A multi-zone digital-to-analog device is provided with a digital-to-analog (D/A) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), a clock input to accept a clock signal with a clock frequency of P Hz, and an output to supply an analog value having a bandwidth of M Hz. An upsampling stage has an input to accept the analog value and a clock input to accept the clock signal. The upsampling stage has a device bandwidth of L Hz to supply an analog output signal with a full power bandwidth of K Hz, where (P/2)=M and M<K<L. The upsampling stage supplies analog output signal images in a plurality of Nyquist zones. In one aspect, the D/A stage supplies N deinterleaved analog values having a combined bandwidth of M Hz, where N×(P/2)=M.Type: GrantFiled: June 20, 2018Date of Patent: December 3, 2019Assignee: IQ-Analog CorporationInventors: Michael Kappes, Steven R. Norsworthy, Costantino Pala
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Patent number: 10461764Abstract: A system and method are provided for calibrating an interleaved digital-to-analog converter (DAC). Sets of sub-DACs are enabled, and by creating a high frequency fundamental signal, spurs can be driven down sufficiently low in frequency to be sampled and digitally converted. By minimizing the power of these digital signals, the duty cycles of the different clock phases are calibrated. Then, sets of sub-DACs are enabled and high pass filtered, so that the spurs can be downconverted using corresponding phases of the clock, to a frequency low enough to sampled and digitally converted. The power of the digital signals is minimized as a first step in phase calibration. As a final step, all the sub-DACs are enabled, the high pass filter removed, and a high frequency fundamental signal is downconverted using at least two clock phases, so that the phase difference can be measured and corrected.Type: GrantFiled: June 4, 2019Date of Patent: October 29, 2019Assignee: IQ-Analog CorporationInventors: Pedro Emiliano Paro Filho, Costantino Pala
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Publication number: 20190013821Abstract: A multi-zone digital-to-analog device is provided with a digital-to-analog (D/A) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), a clock input to accept a clock signal with a clock frequency of P Hz, and an output to supply an analog value having a bandwidth of M Hz. An upsampling stage has an input to accept the analog value and a clock input to accept the clock signal. The upsampling stage has a device bandwidth of L Hz to supply an analog output signal with a full power bandwidth of K Hz, where (P/2)=M and M<K<L. The upsampling stage supplies analog output signal images in a plurality of Nyquist zones. In one aspect, the D/A stage supplies N deinterleaved analog values having a combined bandwidth of M Hz, where N×(P/2)=M.Type: ApplicationFiled: June 20, 2018Publication date: January 10, 2019Inventors: Michael Kappes, Steven R. Norsworthy, Costantino Pala
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Patent number: 10033398Abstract: A multi-zone digital-to-analog device is provided with a digital-to-analog (D/A) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), a clock input to accept a clock signal with a clock frequency of P Hz, and an output to supply an analog value having a bandwidth of M Hz. An upsampling stage has an input to accept the analog value and a clock input to accept the clock signal. The upsampling stage has a device bandwidth of L Hz to supply an analog output signal with a full power bandwidth of K Hz, where (P/2)=M and M<K<L. The upsampling stage supplies analog output signal images in a plurality of Nyquist zones. In one aspect, the D/A stage supplies N deinterleaved analog values having a combined bandwidth of M Hz, where N×(P/2)=M.Type: GrantFiled: October 18, 2017Date of Patent: July 24, 2018Assignee: IQ-Analog CorporationInventors: Michael Kappes, Steven R. Norsworthy, Costantino Pala
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Patent number: 9035810Abstract: A system and method are provided for measuring current sources, such as might be useful in the calibration of a digital-to-analog converter (DAC). The method provides a first plurality of current sources. Each current source is engageable to supply a current representing a corresponding nominal value. The method selectively enables current source combinations of current. In response to measuring the current source combinations, current difference values are found, and the current source nominal values are adjusted using the current difference values. In one aspect, a reference current source is provided having a reference first value, and the current source nominal values are adjusted with respect to the reference first value. The current sources may have corresponding nominal digital values adjusted using measured digital difference values.Type: GrantFiled: January 21, 2015Date of Patent: May 19, 2015Assignee: IQ—Analog CorporationInventors: Mikko Waltari, Costantino Pala
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Patent number: 7737875Abstract: An input signal is compared to 2N?1 reference voltages to generate 2N?1 corresponding binary valued comparison signals, delaying at least one of the comparison signals by a variable delay and detecting a difference in arrival time between the delayed signal and another comparison signal. A time interpolation signal encoding a plurality of bins within a least significant bit quantization level is generated, based on the detected difference in arrival time. An M-bit output data is generated based on the comparison signals and the time interpolation signal. A non-uniformity of a code density of the M-bit output data is detected, and based on the detecting the delaying is varied.Type: GrantFiled: November 13, 2008Date of Patent: June 15, 2010Assignee: NXP B.V.Inventors: Mikko Waltari, Costantino Pala
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Patent number: 7701374Abstract: A system for determining an optimal sampling phase is provided. The system includes a plurality of analog to digital converters, each receiving an analog signal and a clock phase signal and generating an output. A clock generator receives a reference clock and generates a plurality of clock phase signals. A sampling phase system receives the plurality of outputs of the analog to digital converters and generates an optimal sampling phase.Type: GrantFiled: February 26, 2008Date of Patent: April 20, 2010Assignee: Conexant Systems, Inc.Inventor: Costantino Pala
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Publication number: 20090212824Abstract: A system for determining an optimal sampling phase is provided. The system includes a plurality of analog to digital converters, each receiving an analog signal and a clock phase signal and generating an output. A clock generator receives a reference clock and generates a plurality of clock phase signals. A sampling phase system receives the plurality of outputs of the analog to digital converters and generates an optimal sampling phase.Type: ApplicationFiled: February 26, 2008Publication date: August 27, 2009Inventor: Costantino Pala
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Publication number: 20090153388Abstract: An input signal is compared to 2N?1 reference voltages to generate 2N?1 corresponding binary valued comparison signals, delaying at least one of the comparison signals by a variable delay and detecting a difference in arrival time between the delayed signal and another comparison signal. A time interpolation signal encoding a plurality of bins within a least significant bit quantization level is generated, based on the detected difference in arrival time. An M-bit output data is generated based on the comparison signals and the time interpolation signal. A non-uniformity of a code density of the M-bit output data is detected, and based on the detecting the delaying is varied.Type: ApplicationFiled: November 13, 2008Publication date: June 18, 2009Applicant: NXP B.V.Inventors: Mikko WALTARI, Costantino Pala