Abstract: An integrated circuit manufacturing method uses chemical-mechanical polishing (CMP) to planarize a nonplanar submetal (or intermetal) silica dielectric layer. The planarized device is cleaned with an aqueous solution of ammonium hydroxide and citric acid. Exposed hydrated silica is etched using mixture of nitric and hydrofluoric acids, freeing embedded contaminants from the CMP slurry. The hydrofluroic acid is the etching agent, while the nitric acid combines with the freed contaminants to render water soluble products. They are thus carried away in an aqueous rinse, whereas otherwise they might recontaminate the device. A metal interconnect structure is formed on the etched oxide by forming contact apertures, depositing metal, and patterning the metal. The method can be applied also to nonplanar intermetal dielectrics and subsequent metal interconnect layers. The result is an integrated manufacturing method with higher yields and a more reliable manufactured integrated circuit.

Abstract: A purge process for an LPCVD TEOS silicon dioxide deposition method uses a series of five purge cycles to allow low-defect wafer processing with less frequent chamber removal and cleaning. The purge process begins by loading dummy wafers into the chamber. Chamber pressure is reduced to below 20 mTorr. A maximal nonreactant gas flow for two minutes is used to dislodge and carry away contaminants such as flakes from silicon dioxide previously deposited on the chamber wall. After the first four of five purge cycles, the method returns to the reduction of chamber pressure, e.g., by maintaining the vacuum on while the gas sources are turned off. After the fifth cycle, the chamber is slowly filled with nitrogen until ambient pressure is reached. Then the dummy wafers are removed. The system is then ready for processing product wafers with reduced particle counts. The purge process is benign in that it only uses equipment and procedures of the type used during product wafer processing.

Abstract: A quartz tube with multiple thermocouple ports arranged along its radius allows for the quartz tube to be rotated while the thermocouple is always placed in the bottom position of the quartz tube. This avoids a problem of the sagging of the quartz tube. When quartz tubes are not rotated, the quartz tubes tend to start sagging from their top. By rotating the quartz tube different portions of the quartz tube are at the top at different times. By using multiple thermocouple ports arranged around the radius of the quartz tube, the thermocouple can be positioned at the bottom of the quartz tube for different orientations of the quartz tube.

Abstract: A semiconductor deposition system with thermal trap characterized by a processing chamber, a source of process gas coupled to an inlet of the processing chamber, a thermal trap coupled to an outlet of the processing chamber, and a pump mechanism operative to pump a gas from the process chamber and into the thermal trap. The thermal trap preferably includes an enclosure defining a trap chamber, where an inlet to the trap chamber is coupled to the outlet of the processing chamber, a condensable-solid collection surface located within the trap chamber, a mechanism for maintaining the temperature of the collection surface at or below the temperature at which a gas flowing into the chamber condenses into a solid form, and a mechanism for maintaining the temperature of an inner surface of the enclosure at a temperature above which the gas condenses into a solid form.