Patents by Inventor Craig Hampel

Craig Hampel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220171721
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.
    Type: Application
    Filed: December 11, 2021
    Publication date: June 2, 2022
    Inventors: Frederick A. Ware, Kenneth L. Wright, John Eric Linstadt, Craig Hampel
  • Patent number: 11328764
    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: May 10, 2022
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Ely Tsern, Craig Hampel
  • Patent number: 11210242
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: December 28, 2021
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Kenneth L. Wright, John Eric Linstadt, Craig Hampel
  • Publication number: 20210375351
    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.
    Type: Application
    Filed: May 18, 2021
    Publication date: December 2, 2021
    Inventors: Ian Shaeffer, Ely Tsern, Craig Hampel
  • Patent number: 11043258
    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: June 22, 2021
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Ely Tsern, Craig Hampel
  • Publication number: 20210035652
    Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 4, 2021
    Inventors: Craig Hampel, Mark Horowitz
  • Publication number: 20200364164
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.
    Type: Application
    Filed: May 29, 2020
    Publication date: November 19, 2020
    Inventors: Frederick A. Ware, Kenneth L. Wright, John Eric Linstadt, Craig Hampel
  • Patent number: 10755794
    Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 25, 2020
    Assignee: Rambus Inc.
    Inventors: Craig Hampel, Mark Horowitz
  • Publication number: 20200234756
    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.
    Type: Application
    Filed: April 7, 2020
    Publication date: July 23, 2020
    Inventors: Ian Shaeffer, Ely Tsern, Craig Hampel
  • Publication number: 20200194052
    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.
    Type: Application
    Filed: November 22, 2019
    Publication date: June 18, 2020
    Inventors: Ian Shaeffer, Ely Tsern, Craig Hampel
  • Patent number: 10678719
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 9, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Kenneth L. Wright, John Eric Linstadt, Craig Hampel
  • Patent number: 10672458
    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: June 2, 2020
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Ely Tsern, Craig Hampel
  • Patent number: 10535398
    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: January 14, 2020
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Ely Tsern, Craig Hampel
  • Publication number: 20190259447
    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.
    Type: Application
    Filed: December 10, 2018
    Publication date: August 22, 2019
    Inventors: Ian Shaeffer, Ely Tsern, Craig Hampel
  • Patent number: 10381067
    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 13, 2019
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Ely Tsern, Craig Hampel
  • Publication number: 20180267911
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.
    Type: Application
    Filed: September 9, 2016
    Publication date: September 20, 2018
    Inventors: Frederick A. Ware, Kenneth L. Wright, John Eric Linstadt, Craig Hampel
  • Publication number: 20180137909
    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.
    Type: Application
    Filed: December 5, 2017
    Publication date: May 17, 2018
    Inventors: Ian Shaeffer, Ely Tsern, Craig Hampel
  • Patent number: 9865329
    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 9, 2018
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Ely Tsern, Craig Hampel
  • Publication number: 20170365354
    Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.
    Type: Application
    Filed: August 30, 2017
    Publication date: December 21, 2017
    Inventors: Craig Hampel, Mark Horowitz
  • Patent number: 9767918
    Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A defect circuit may generate the control signal in view of a detection of a defect in the nonvolatile memory device based on a comparison of a test value read from a memory location to a stored value.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 19, 2017
    Assignee: Rambus Inc.
    Inventors: Craig Hampel, Mark Horowitz