Patents by Inventor Cyrille Le Royer
Cyrille Le Royer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240341201Abstract: A method for making a device with superconductor qubit(s) including at least one JoFET formed by the following steps of: making, over a semiconductor layer, a protective dielectric portion arranged over a first region of the semiconductor layer; implanting dopants in second regions adjacent to the first region; depositing a protective dielectric layer covering the protective dielectric portion and the second regions; exposing the protective dielectric layer to a laser pulse; and wherein the materials and the thicknesses of the protective dielectric portion and of the protective dielectric layer are selected so as to prevent the laser pulse from reaching the first region, and melting the semiconductor of the second regions which forms, after cooling, a recrystallised semiconductor material having superconductor material properties.Type: ApplicationFiled: April 21, 2023Publication date: October 10, 2024Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Cyrille LE ROYER, Fabrice NEMOUCHI, Nicolas POSSEME, Sébastien KERDILES, François LEFLOCH
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Publication number: 20240162299Abstract: A field effect transistor includes a substrate; an electron channel layer disposed on the substrate; a barrier layer disposed on the electron channel layer; a hole channel layer disposed on the barrier layer; a p-type doped semiconductor material layer disposed on the hole channel layer; a source electrode including a first portion in ohmic contact with the electron channel layer and a second portion in ohmic contact with the p-type doped semiconductor material layer; a drain electrode in ohmic contact with the electron channel layer; and a gate electrode disposed facing the p-type doped semiconductor material layer, between the source and drain electrodes.Type: ApplicationFiled: August 1, 2023Publication date: May 16, 2024Inventors: Julien BUCKLEY, René ESCOFFIER, Cyrille LE ROYER, Blend MOHAMAD
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Patent number: 11941485Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.Type: GrantFiled: November 24, 2021Date of Patent: March 26, 2024Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Nicolas Posseme, Louis Hutin, Cyrille Le Royer, François Lefloch, Fabrice Nemouchi, Maud Vinet
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Patent number: 11854805Abstract: A method for forming SiGe-based regions with different Ge concentrations is provided. After defining the regions 1, 2 on a SOI substrate, a grating of masking patterns is formed on at least one region 2. After the epitaxial growth of a Ge-based layer in each of the regions, a first vertical diffusion is carried out. A second horizontal diffusion is then carried out such that the Ge diffuses beneath the masking patterns of the region 2. Thus, the region 2 has a Ge concentration that is lower than the Ge concentration of the region 1.Type: GrantFiled: January 26, 2022Date of Patent: December 26, 2023Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Joël Kanyandekwe, Cyrille Le Royer
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Publication number: 20230210021Abstract: The invention concerns an inteconnect device for interconnection between lines of superconducting material at least one via in contact with those lines, comprising: a) a first substrate, which carries at least one first line of a first superconducting material; b) at least one first via of a second superconducting material, different from the first superconducting material, said at least one first line being disposed between said first substrate and said first via; c) at least one second line above said first via and in contact with the latter.Type: ApplicationFiled: November 17, 2022Publication date: June 29, 2023Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Nicolas POSSEME, Cyrille LE ROYER, Fabrice NEMOUCHI, Roselyne SEGAUD
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Publication number: 20230186136Abstract: A method for producing a quantum device comprising forming a supraconductive layer, forming a mask on the supraconductive layer, the mask comprising masking patterns and at least two openings alternately in a direction, the at least two openings being separated from one another by a separation distance pi (i=1 . . . n), and further each having a width di (i=1 . . . n+1), such as the separation distance pi and a width di are less than a coherence length of a Cooper pair in said supraconductive material, and modifying, through the at least two openings, of the exposed portions of the supraconductive layer, so as to form at least two barriers of width di separating the supraconductive regions.Type: ApplicationFiled: November 21, 2022Publication date: June 15, 2023Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Cyrille LE ROYER, François LEFLOCH, Fabrice NEMOUCHI, Nicolas POSSEME
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Publication number: 20230120901Abstract: A semiconductor device made on a substrate including an active region and a non-active region at least partially surrounding the active region, a plurality of gate stacks, a part of each gate stack being on the active region, each gate stack being separated from adjacent gate stacks by a spacer by a distance e, the device being such that, for each gate stack, the part of the gate stack located on the active region has a height h2, the part of the same gate stack located on the non-active region has a height h1, and h2/e=a2 and h1/e=a1<alim where a2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap is in the spacer, and a1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap is in the spacer.Type: ApplicationFiled: October 14, 2022Publication date: April 20, 2023Inventors: Fabrice NEMOUCHI, Cyrille LE ROYER, Nicolas POSSEME
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Publication number: 20220384573Abstract: A method for manufacturing a pFET transistor, the method for manufacturing the transistor including providing a base structure comprising a silicon channel and a gate structure, the gate structure surrounding the channel leaving two flanks of the channel free; growing a first layer made from silicon-germanium alloy on the flanks of the channel; enriching the channel with germanium atoms from the first layer; and forming a drain region and a source region on either side of the channel.Type: ApplicationFiled: May 27, 2022Publication date: December 1, 2022Inventors: Cyrille LE ROYER, Joël KANYANDEKWE, Sylvain BARRAUD
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Patent number: 11515148Abstract: Method for producing a semiconductor device, including: producing, on a first region of a surface layer comprising a first semiconductor and disposed on a buried dielectric layer, a layer of a second compressive strained semiconductor along a first direction; etching a trench through the layer of the second semiconductor forming an edge of a portion of the layer of the second semiconductor oriented perpendicularly to the first direction, and wherein the bottom wall is formed by the surface layer; thermal oxidation forming in the surface layer a semiconductor compressive strained portion along the first direction and forming in the trench an oxide portion; producing, through the surface layer and/or the oxide portion, and through the buried dielectric layer, dielectric isolation portions around an assembly formed of the compressive strained semiconductor portion and the oxide portion; and wherein the first semiconductor is silicon, the second semiconductor is SiGe, and said at least one compressive strainedType: GrantFiled: June 29, 2020Date of Patent: November 29, 2022Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Loic Gaben, Cyrille Le Royer, Fabrice Nemouchi, Nicolas Posseme, Shay Reboh
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Publication number: 20220310394Abstract: A method for forming crystalline SiC-based regions on either side of an N-type transistor channel, including: providing a substrate including a silicon-based layer having a thickness e, forming at least one masking pattern on the silicon-based layer, with the at least one masking pattern having openings, with the openings corresponding to implantation regions of the silicon-based layer, amorphising the silicon-based layer through the openings of the at least one masking pattern, in the implantation regions, to a depth d strictly less than the thickness e, so as to form amorphised implantation regions in the silicon-based layer, implanting carbon into amorphous implantation regions, performing thermal recrystallisation annealing to turn the amorphised implantation regions into crystalline SiC-based regions, the method including: after forming the crystalline SiC-based regions, forming a transistor gate on the silicon-based layer, directly at the edge of the crystalline SiC-based regions.Type: ApplicationFiled: March 24, 2022Publication date: September 29, 2022Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Joël KANYANDEKWE, Cyrille LE ROYER
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Publication number: 20220238338Abstract: A method for forming SiGe-based regions with different Ge concentrations is provided. After defining the regions 1, 2 on a SOI substrate, a grating of masking patterns is formed on at least one region 2. After the epitaxial growth of a Ge-based layer in each of the regions, a first vertical diffusion is carried out. A second horizontal diffusion is then carried out such that the Ge diffuses beneath the masking patterns of the region 2. Thus, the region 2 has a Ge concentration that is lower than the Ge concentration of the region 1.Type: ApplicationFiled: January 26, 2022Publication date: July 28, 2022Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Joël KANYANDEKWE, Cyrille LE ROYER
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Publication number: 20220231147Abstract: A semiconductor device includes a substrate; a plurality of gate stacks situated horizontally following one another on the substrate, each gate stack including a layer of a dielectric material in contact with the substrate and a layer of a conductive material on the layer of dielectric material; a source and a drain situated on the substrate on either side of the plurality of gate stacks; a plurality of first spacers made of a first dielectric material, called secondary spacers, having a first width, called width of the secondary spacers, the source and the drain being separated from the closest gate stack by a secondary spacer; at least one main spacer made of a second dielectric material, a main spacer being situated between each gate stack, the width of the main spacer(s) being greater than the width of the secondary spacers.Type: ApplicationFiled: January 18, 2022Publication date: July 21, 2022Inventors: Cyrille LE ROYER, Louis HUTIN, Fabrice NEMOUCHI, Nicolas POSSEME
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Patent number: 11387147Abstract: A method is provided for producing a component based on a plurality of transistors on a substrate including an active area and an electrical isolation area, each transistor including a gate and spacers on either side of the gate, the electrical isolation area including at least one cavity formed as a hollow between a spacer of a first transistor of the plurality of transistors and a spacer of a second transistor of the plurality of transistors, the first and the second transistors being adjacent, the method including: forming the gates of the transistors; forming the spacers; and forming a mechanically constraining layer for the transistors; and after forming the spacers and before forming the mechanically constraining layer, forming a filling configured to at least partially fill, with a filling material, the at least one cavity within the electrical isolation area, between the spacers of the first and the second transistors.Type: GrantFiled: August 10, 2020Date of Patent: July 12, 2022Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Nicolas Posseme, Cyrille Le Royer, Fabrice Nemouchi
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Patent number: 11362181Abstract: A process for fabricating an electronic component with multiple quantum dots is provided, including providing a stack including a substrate, a nanostructure made of semiconductor material superposed over the substrate and including first and second quantum dots and a link linking the quantum dots, first and second control gate stacks arranged on the quantum dots, the gate stacks separated by a gap, the quantum dots and the link having a same thickness; partially thinning the link while using the gate stacks as masks to obtain the link, a thickness of which is less than that of the quantum dots; and conformally forming a dielectric layer on either side of the gate stacks so as to fill the gap above the partially thinned link. An electronic component with multiple quantum dots is also provided.Type: GrantFiled: November 29, 2019Date of Patent: June 14, 2022Assignee: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Nicolas Posseme, Louis Hutin, Cyrille Le Royer, Fabrice Nemouchi
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Publication number: 20220173229Abstract: A quantum device includes a transistor pattern carried by a substrate, the transistor pattern having, in a stack, a gate dielectric and a superconducting gate on the gate dielectric. The superconducting gate has a base, a tip, sidewalls and at least one superconducting region made of a material that has, as a main component, at least one superconducting element. The superconducting gate also includes a basal portion having a dimension, taken in a first direction of a basal plane that is smaller than a dimension of the tip of the superconducting gate. The transistor pattern further includes at least one dielectric portion made of a dielectric material in contact with the top face of the gate dielectric and the basal portion of the superconducting gate.Type: ApplicationFiled: November 24, 2021Publication date: June 2, 2022Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Nicolas POSSEME, Louis HUTIN, Cyrille LE ROYER, François LEFLOCH, Fabrice NEMOUCHI, Maud VINET
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Publication number: 20220172093Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.Type: ApplicationFiled: November 24, 2021Publication date: June 2, 2022Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Nicolas POSSEME, Louis HUTIN, Cyrille LE ROYER, François LEFLOCH, Fabrice NEMOUCHI, Maud VINET
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Patent number: 11217446Abstract: A process for fabricating an integrated circuit is provided, including steps of providing a substrate including a silicon layer, a layer of insulator a layer of hard mask and accesses to first and second regions of the silicon layer; forming first and second deposits of SiGe alloy on the first and the second regions in order to form first and second stacks; then protecting the first deposit and maintaining an access to the second deposit; then performing an etch in order to form trenches between the hard mask and two opposite edges of the second stack; then forming a tensilely strained silicon layer in the second region via amorphization of the second region; then crystallization; and enriching the first region in germanium by diffusion from the first deposit.Type: GrantFiled: December 17, 2019Date of Patent: January 4, 2022Assignee: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Nicolas Posseme, Loic Gaben, Cyrille Le Royer, Fabrice Nemouchi, Shay Reboh
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Patent number: 11121043Abstract: There is provided a method for producing, on one same wafer, at least one first transistor surmounted at least partially on a voltage stressed layer and a second transistor surmounted at least partially on a compression stressed layer, the method including providing a wafer including the first and the second transistors; forming at least one stressed nitride-based layer, on the first and the second transistors, the layer being voltage stressed; depositing a protective layer so as to cover a first zone of the layer, the first zone covering at least partially the first transistor and leaving a second zone of the layer uncovered, the second zone at least partially covering the second transistor; and modifying a type of stress of the second zone of the layer by implanting hydrogen-based ions from a plasma in the second zone, such that the second zone of the layer is compression stressed.Type: GrantFiled: December 21, 2018Date of Patent: September 14, 2021Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Nicolas Posseme, Cyrille Le Royer, Yves Morand
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Patent number: 11081399Abstract: A method is provided for producing a microelectronic component on a substrate including in an exposed manner on a first face thereof, an active zone and an electrical isolation zone adjacent thereto, the method including forming a gate on the active zone, forming spacers each configured to cover a surface of a different edge of the gate, and forming source and drain zones by doping portions of the active zone adjacent to the gate, the method successively including forming a first layer of spacer material above the active zone and the electrical isolation zone; an ion implantation to produce doping of the portions through the first layer; removing a modified portion of the first layer disposed overlooking the portions, the modified portion coming from the ion implantation, the removing being configured to preserve at least part of the first layer at a level of edges of the gate.Type: GrantFiled: December 12, 2019Date of Patent: August 3, 2021Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Nicolas Posseme, Cyrille Le Royer
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Publication number: 20210066133Abstract: A method is provided for producing a component based on a plurality of transistors on a substrate including an active area and an electrical isolation area, each transistor including a gate and spacers on either side of the gate, the electrical isolation area including at least one cavity formed as a hollow between a spacer of a first transistor of the plurality of transistors and a spacer of a second transistor of the plurality of transistors, the first and the second transistors being adjacent, the method including: forming the gates of the transistors; forming the spacers; and forming a mechanically constraining layer for the transistors; and after forming the spacers and before forming the mechanically constraining layer, forming a filling configured to at least partially fill, with a filling material, the at least one cavity within the electrical isolation area, between the spacers of the first and the second transistors.Type: ApplicationFiled: August 10, 2020Publication date: March 4, 2021Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Nicolas POSSEME, Cyrille LE ROYER, Fabrice NEMOUCHI