Abstract: Various implementations described herein are related to a device having memory circuitry activated by a power-gated supply. The device may include level shifting circuitry that receives a switch control signal in a first voltage domain, shifts the switch control signal in the first voltage domain to a second voltage domain, and provides the switch control signal in the second voltage domain. The device may include power-gating circuitry activated by the switch control signal in the second voltage domain, and the power-gating circuitry may provide the power-gated supply to the memory circuitry to trigger activation of the memory circuitry with the power-gated supply when activated by the switch control signal in the second voltage domain.

Abstract: Various implementations described herein are directed to a method that tests and repairs memory fabricated on a wafer or a package. The method may generate and store a reuse table based on memory repair results. The method may manufacture the memory after repairing the memory. The method may access and reuse data stored in the reuse table to repair the memory after manufacturing the memory.

Abstract: Various implementations described herein refer to a device having an encoder coupled to memory. The ECC encoder receives input data from memory built-in self-test circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to memory. The device may have an ECC decoder coupled to memory. The ECC decoder reads the encoded data from memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output. The ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data.

Abstract: An apparatus is provided having a memory device and associated access control circuitry, and an additional memory device and associated additional access control circuitry. Redundant data generation circuitry generates, for a given block of data having an associated given memory address, an associated block of redundant data for use in an error detection process. The access control circuitry is arranged to store, at a location in the memory device determined from the given memory address, at least a portion of the given block of data and a first copy of the associated block of redundant data, and the additional access control circuitry is arranged to store, at a location in the additional memory device determined from the given memory address, any remaining portion of the given block of data not stored in the memory device and a second copy of the associated block of redundant data.

Abstract: Various implementations described herein are related to a device having memory circuitry activated by a power-gated supply. The device may include level shifting circuitry that receives a switch control signal in a first voltage domain, shifts the switch control signal in the first voltage domain to a second voltage domain, and provides the switch control signal in the second voltage domain. The device may include power-gating circuitry activated by the switch control signal in the second voltage domain, and the power-gating circuitry may provide the power-gated supply to the memory circuitry to trigger activation of the memory circuitry with the power-gated supply when activated by the switch control signal in the second voltage domain.

Abstract: Various implementations described herein are related to a device having memory circuitry activated by a power-gated supply. The device may include level shifting circuitry that receives a switch control signal in a first voltage domain, shifts the switch control signal in the first voltage domain to a second voltage domain, and provides the switch control signal in the second voltage domain. The device may include power-gating circuitry activated by the switch control signal in the second voltage domain, and the power-gating circuitry may provide the power-gated supply to the memory circuitry to trigger activation of the memory circuitry with the power-gated supply when activated by the switch control signal in the second voltage domain.

Abstract: Various implementations described herein are related to a device having a sense amplifier that provides output data based on sensing a difference between input signals. The device may have a tracking circuit that tracks a resistive state of a bitcell and provides an input signal to the sense amplifier based on the tracked resistive state of the bitcell. The device may have a bitcell circuit that senses a data value associated with the resistive state of the bitcell and provides another input signal to the sense amplifier based on the sensed data value of the bitcell.

Abstract: Various implementations described herein are related to a device having a sense amplifier that provides output data based on sensing a difference between input signals. The device may have a tracking circuit that tracks a resistive state of a bitcell and provides an input signal to the sense amplifier based on the tracked resistive state of the bitcell. The device may have a bitcell circuit that senses a data value associated with the resistive state of the bitcell and provides another input signal to the sense amplifier based on the sensed data value of the bitcell.

Abstract: Various implementations described herein refer to an integrated circuit having first circuitry and second circuitry. The first circuitry receives first input data and bypasses error correction circuitry to determine whether the first input data has one or more first errors. The second circuitry receives second input data and enables the error correction circuitry to determine whether the second input data has one or more second errors.

Abstract: Various implementations described herein are related to a device having memory circuitry activated by a power-gated supply. The device may include level shifting circuitry that receives a switch control signal in a first voltage domain, shifts the switch control signal in the first voltage domain to a second voltage domain, and provides the switch control signal in the second voltage domain. The device may include power-gating circuitry activated by the switch control signal in the second voltage domain, and the power-gating circuitry may provide the power-gated supply to the memory circuitry to trigger activation of the memory circuitry with the power-gated supply when activated by the switch control signal in the second voltage domain.

Abstract: Various implementations described herein are directed to an implementation of a higher order multiplexer using lower order multiplexers. In an embodiment, the implementation requires a slight modification to the existing circuitry design of the lower multiplexers. A plurality of multiplexers may be coupled with each other such that a common input port and output port is formed. Using an enable signal, only one of the coupled multiplexers may be enabled at a time while the remaining multiplexers are switched off. Therefore, upon receiving a select signal indicating an address of a memory cell, the lower multiplexers coupled together function as a higher order multiplexer in selecting the appropriate column corresponding to the memory cell.

Abstract: Various implementations described herein are directed to device having a memory block and a sense amplifier coupled to the memory block. The device may include a bias generator that applies a bias signal to the sense amplifier for regulating read current to the sense amplifier for faster activation of the memory block.

Abstract: Various implementations described herein are directed to device having a clock generator that provides write reference signals. The device may include a voltage divider that receives the write reference signals and provides an output reference signal based on write polarity of the write reference signals. The device may include a voltage regulator that receives the output reference signal and provides a regulated voltage to a load based on the output reference signal.

Abstract: Briefly, embodiments of claimed subject matter relate to circuits and methods for providing signals, such as signals to bring about writing of binary logic values to magnetic random-access memory (MRAM) cells. In particular embodiments, such circuits may operate to control output signal variability over an operating temperature range.

Abstract: In a particular implementation, an apparatus including first and second bias circuits and an inner amplifier provides sense amplifier offset cancellation. The inner amplifier includes: first and second current generators configured to replicate respective first and second currents from the first and second bias circuits, first and second transistors configured to transform the first and second currents into voltage samples, and first and second capacitors configured to store the voltage samples. In a sampling phase, a sampling of the first and second currents may be performed in the inner amplifier, and further, in an amplification phase, an amplification of the stored voltage samples may also be performed in the inner amplifier.

Abstract: Various implementations described herein are directed to an implementation of a higher order multiplexer using lower order multiplexers. In an embodiment, the implementation requires a slight modification to the existing circuitry design of the lower multiplexers. A plurality of multiplexers may be coupled with each other such that a common input port and output port is formed. Using an enable signal, only one of the coupled multiplexers may be enabled at a time while the remaining multiplexers are switched off. Therefore, upon receiving a select signal indicating an address of a memory cell, the lower multiplexers coupled together function as a higher order multiplexer in selecting the appropriate column corresponding to the memory cell.

Abstract: According to certain implementations of the present disclosure, an input circuit provides one or more reference paths and bit paths for sense amplifier circuit operations. In one implementation, the input circuit includes a reference path, a bit path, and a CMOS resistor. The reference path includes a first MTJ device and a first access device, where the reference path is coupled to the sense amplifier via a first input terminal. The bit path includes a second MTJ device and a second access device, where the bit path is coupled to the sense amplifier via a second input terminal. In certain implementations, the CMOS resistor is coupled to one of the reference path or the bit path.

Abstract: Briefly, embodiments of claimed subject matter relate to adjusting, such as extending, a clock signal to permit completion of a write operations to a first memory type and/or to permit completion of read operations from a second memory type, wherein the first memory type and the second memory type are dissimilar from each other. In certain embodiments, the first memory type may comprise a magnetic random-access memory (MRAM) cell array, and the second memory type may comprise a static random-access memory (SRAM) cell array.

Abstract: In a particular implementation, a circuit comprises: a first branch comprising a first transistor, where the first branch is configured to generate a first voltage; a second branch comprising a second transistor, where the second branch is configured to generate a second voltage; and a comparator configured to generate an output signal based on a comparison of the first and second voltages. Also, the output signal may be configured to regulate an output voltage of one or more negative charge pump circuits coupled to the circuit.

Abstract: Various implementations described herein are directed to device having a memory block and a sense amplifier coupled to the memory block. The device may include a bias generator that applies a bias signal to the sense amplifier for regulating read current to the sense amplifier for faster activation of the memory block.