Patents by Inventor Da Huang

Da Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230135496
    Abstract: A test method is configured to test a chip on a circuit under test, wherein the circuit under test further includes a DC-DC converter. The test method includes the operations of: generating a test pulse signal; filtering the test pulse signal to generate a first test DC voltage to the DC-DC converter, wherein the DC-DC converter transforms the first test DC voltage to a second test DC voltage and transmits the second test DC voltage to the chip; and extracting an output signal of the chip to determine a performance of the chip, wherein the chip generates the output signal according to the second test DC voltage.
    Type: Application
    Filed: October 20, 2022
    Publication date: May 4, 2023
    Inventors: CHIA HAN LIN, MENG AN KUO, ZONG-DA HUANG
  • Publication number: 20230080475
    Abstract: Nanogels and methods of synthesizing and using these nanogels are provided. The nanogels are formed by mixing a building block (e.g., polymer), crosslinker, preferably a target (e.g., biomedical compound or molecule), and a solvent in a multi-inlet vortex mixer, so as to cause the polymer and crosslinker to react and form a chemically crosslinked polymer network. In embodiments including a target, the target will be interspersed in and among that network and can be physically embedded and/or chemically bound therein.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 16, 2023
    Inventors: Hu Yang, Da Huang
  • Publication number: 20230067696
    Abstract: A semiconductor device comprising a semiconductor channel, an epitaxial structure coupled to the semiconductor channel, and a gate structure electrically coupled to the semiconductor channel. The semiconductor device further comprises a first interconnect structure electrically coupled to the epitaxial structure and a dielectric layer that contains nitrogen. The dielectric layer comprises a first portion protruding from a nitrogen-containing dielectric capping layer that overlays either the gate structure or the first interconnect structure.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Yi-Shan Chen, Kuan-Da Huang, Han-Yu Lin, Li-Te Lin, Ming-Huan Tsai
  • Publication number: 20230061082
    Abstract: In some embodiments, the present disclosure relates to a method for manufacturing an integrated chip. The method includes forming a transistor structure over a substrate. The transistor structure comprises a pair of source/drain regions and a gate electrode between the source/drain regions. A lower inter-level dielectric (ILD) layer is formed over the pair of source/drain regions and around the gate electrode. A gate capping layer is formed over the gate electrode. A selective etch and deposition process is performed to form a dielectric protection layer on the gate capping layer while forming a contact opening within the lower ILD layer. A lower source/drain contact is formed within the contact opening.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Kuan-Da Huang, Hao-Heng Liu, Li-Te Lin
  • Publication number: 20230027972
    Abstract: An orthopedic insole may include at least one strength layer and at least one shock absorbing layer. In one embodiment, the strength layer may be relatively rigid and includes a heel portion and an arch portion, contoured to fit the plantar or bottom surface of the foot to provide arch support. The shock absorbing layer may include a plurality of shock absorbing cells such as recoverable honeycombs or any other negative stiffness structure with the capability to recover. A gait analysis that may include an individual's weight transfer trajectory may have to be conducted to determine the structure of the shock absorbing layer. The orthopedic insole may further include an adjusting layer to supplement the strength layer and the shock absorbing layer to make adjustment to the orthopedic insole if needed.
    Type: Application
    Filed: October 1, 2022
    Publication date: January 26, 2023
    Inventor: Li-Da Huang
  • Publication number: 20220416537
    Abstract: A power supply circuit is configured to supply power to a display panel. The power supply circuit includes a receiver circuit and a transmitter circuit. The receiver circuit is configured to couple the display panel and output a hot plugging signal. The transmitter circuit is configured to receive the hot plugging signal and couple a power circuit. The transmitter circuit is further configured to communicate the receiver circuit to generate an enable signal. The hot plugging signal and the enable signal are configured to control whether a first voltage signal from the power circuit is transmitted to the receiver circuit and the display panel via the transmitter circuit.
    Type: Application
    Filed: March 22, 2022
    Publication date: December 29, 2022
    Inventors: Ching-Lan YANG, Zong-Da HUANG, Chun-Yuan HUANG
  • Publication number: 20220231024
    Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate. The substrate includes a first region, a second region, and an isolation region between the first region and the second region. The semiconductor structure also includes a first fin, a second fin and a third fin disposed over the first region, the second region, and the isolation region, respectively. Further, the semiconductor structure includes a gate structure. The gate structure includes a first work function layer over the first region and a first portion of the isolation region, and a second work function layer over the second region and a second portion of the isolation region. An interface where the first work function layer is in contact with the second work function layer is located over a top surface of the third fin.
    Type: Application
    Filed: January 14, 2022
    Publication date: July 21, 2022
    Inventors: Da HUANG, Yao Qi DONG, Xiaowan DAI, Zhen TIAN
  • Publication number: 20220224557
    Abstract: Various arrangements for using captured voice to generate a custom interface controller are presented. A vocal recording from a user may be captured in which a spoken command and multiple smart-home devices are indicated. One or more common functions that map to the multiple smart-home devices may be determined. A custom interface controller may be generated that controls the one or more common functions of each smart-home device of the multiple smart-home devices.
    Type: Application
    Filed: March 30, 2022
    Publication date: July 14, 2022
    Applicant: Google LLC
    Inventors: Benjamin Brown, Da Huang, Christopher Conover, Lisa Williams, Henry Chung
  • Publication number: 20220199178
    Abstract: When a driving circuit of an anti-fuse memory device programs a selected anti-fuse memory cell, voltage differences between unselected bit lines and unselected anti-fuse control lines would be eliminated or decreased to an acceptable value by floating unselected anti-fuse control lines or by applying a second control line voltage to the unselected anti-fuse control lines. Leakage currents flowing from unselected bit lines through ruptured anti-fuse transistors of the anti-fuse memory device to the unselected anti-fuse control lines would be decreased or eliminated, and program disturbance would be avoided.
    Type: Application
    Filed: September 8, 2021
    Publication date: June 23, 2022
    Applicant: eMemory Technology Inc.
    Inventors: Chieh-Tse Lee, Ting-Yang Yen, Cheng-Da Huang, Chun-Hung Lin
  • Publication number: 20220180207
    Abstract: Provided is an end-to-end pipeline (e.g., which may be implemented in TensorFlow) which leverages a specialized search space to generate custom models which provide improved time series prediction.
    Type: Application
    Filed: March 24, 2021
    Publication date: June 9, 2022
    Inventors: Chen Liang, Da Huang, Yifeng Lu
  • Patent number: 11316709
    Abstract: Various arrangements for integrating control of multiple cloud-based smart-home devices are presented. Registration information may be received for a first and second smart-home device that are controlled using different cloud-based server systems. A determination may be made that that the first smart-home device and the second smart-home device share a common function. The first smart-home device and the second smart-home device may be assigned to a common operating characteristic group based on the common function being shared by the first smart-home device and the second smart-home device. A control element may be provided that allows for control of smart-home devices with the common operating characteristic group. The control element may control the common function at the first smart-home device via the first cloud-based server system and at the second smart-home device via the second cloud-based server system.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: April 26, 2022
    Assignee: Google LLC
    Inventors: Benjamin Brown, Da Huang, Christopher Conover, Lisa Williams, Henry Chung
  • Patent number: 11306363
    Abstract: A microRNA (miRNA) expression signature for predicting triple-negative breast cancer (TNBC) recurrence is provided. The miRNA expression signature consists essentially of hsa-miR-139-5p, hsa-miR-10b-5p, hsa-miR-486-5p, hsa-miR-455-3p, hsa-miR-107, hsa-miR-146b-5p, hsa-miR-324-5p, and hsa-miR-20a-5p.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: April 19, 2022
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Kuang-Wen Liao, Hsien-Da Huang, Hsiao-Chin Hong, Cheng-Hsun Chuang
  • Publication number: 20210404008
    Abstract: A microRNA (miRNA) expression signature for predicting triple-negative breast cancer (TNBC) recurrence is provided. The miRNA expression signature consists essentially of hsa-miR-139-5p, hsa-miR-10b-5p, hsa-miR-486-5p, hsa-miR-455-3p, hsa-miR-107, hsa-miR-146b-5p, hsa-miR-324-5p, and hsa-miR-20a-5p.
    Type: Application
    Filed: June 29, 2020
    Publication date: December 30, 2021
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Kuang-Wen LIAO, Hsien-Da HUANG, Hsiao-Chin HONG, Cheng-Hsun CHUANG
  • Patent number: 11200821
    Abstract: An image processing chip test method comprising: controlling a power supply circuit to provide a first operating voltage to an image processing chip comprising a storage device; and when reading written first image data from the storage device, the test device receives a first error detection code corresponding to the first image data and determines whether the first error detection code means an error occurs. If an error occurs, record the first operating voltage as an erroneous operating voltage, and if the error does not occur, provide a second operating voltage to the image processing chip. Also, when the written second image data is read from the storage device, the test device receives a second error detection code corresponding to the second image data and determines whether the second error detection code means an error occurs.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: December 14, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Zong-Da Huang, Ching-Lan Yang
  • Patent number: 11195262
    Abstract: A method for identifying a body region in a medical image includes obtaining a medical image including a number of consecutive bio-section images, inputting the medical image into a preset machine learning model to obtain a numerical value for each of the bio-section images corresponding to the body region to which the bio-section image belongs, determining whether the numerical values of the medical image are abnormal, adjusting the numerical values when the numerical values are abnormal, determining the body region corresponding to the numerical values or the adjusted numerical values, and labeling the body region in the medical image and outputting the labeled medical image. The bio-section images are cross-sectional images of a living body.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: December 7, 2021
    Assignee: COHESION INFORMATION TECHNOLOGY CORP.
    Inventors: Feng-Mao Lin, Chi-Wen Chen, Wei-Da Huang, Liangtsan Gary Wu
  • Publication number: 20210327318
    Abstract: An image processing chip test method comprising: controlling a power supply circuit to provide a first operating voltage to an image processing chip comprising a storage device; and when reading written first image data from the storage device, the test device receives a first error detection code corresponding to the first image data and determines whether the first error detection code means an error occurs. If an error occurs, record the first operating voltage as an erroneous operating voltage, and if the error does not occur, provide a second operating voltage to the image processing chip. Also, when the written second image data is read from the storage device, the test device receives a second error detection code corresponding to the second image data and determines whether the second error detection code means an error occurs.
    Type: Application
    Filed: September 30, 2020
    Publication date: October 21, 2021
    Inventors: Zong-Da Huang, Ching-Lan Yang
  • Patent number: 11086349
    Abstract: A reference voltage generator includes an output terminal, a current source, a reference circuit, a protection circuit, and a control circuit. The output terminal outputs a reference voltage. The current source is coupled to the output terminal, and generates a reference current. The reference circuit is coupled to the output terminal, and generates a reference voltage according to the reference current. The protection circuit is coupled to the output terminal, and adjusts a voltage of the output terminal to an operating voltage. The control circuit is coupled to the reference circuit and the protection circuit. The control circuit controls the reference circuit and the protection circuit according to a start signal.
    Type: Grant
    Filed: September 1, 2019
    Date of Patent: August 10, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Jen-Yu Peng, Chun-Hung Lin, Cheng-Da Huang
  • Patent number: 11074963
    Abstract: A non-volatile memory includes a memory cell array, an amplifying circuit and a first multiplexer. The memory cell array includes m×n memory cells. The memory cell array is connected with a control line, m word lines and n local bit lines, wherein m and n are positive integers. The amplifying circuit includes n sensing elements. The n sensing elements are respectively connected between the n local bit lines and n read bit lines. The first multiplexer is connected with the n local bit lines and the n read bit lines. According to a first select signal, the first multiplexer selects one of the n local bit lines to be connected with a first main bit line and selects one of the n read bit lines to be connected with a first main read bit line.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: July 27, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Yu-Ping Huang, Chun-Hung Lin, Cheng-Da Huang
  • Patent number: D953402
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: May 31, 2022
    Inventor: Kuan Da Huang
  • Patent number: D956844
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: July 5, 2022
    Inventor: Kuan Da Huang