Abstract: A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage.

Abstract: A semiconductor apparatus includes a power supply changing unit. The power supply changing unit is configured to receive an enable signal and power supply voltage, generate first voltage or second voltage according to the enable signal, change a voltage level of the second voltage according to a level signal, and supply the first voltage or the second voltage as a driving voltage of an internal circuit, wherein the internal circuit receives a first input signal to output a second input signal.

Abstract: A delay circuit includes a clock delay line, a command delay line, a delay line control block, and a shared shift register block. The clock delay line delays an input clock and generates a delayed clock. The command delay line delays a command signal and generates a delayed command signal. The delay line control block generates a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock. The shared shift register block sets delay amounts of the clock delay line and the command delay line to be substantially the same with each other, in response to the control signal.

Abstract: A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information.

Abstract: A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage.

Abstract: A clock generation circuit includes a delay line, which delays an input clock and generates a delayed clock, a delay modeling unit, which delays the delayed clock by a modeled delay value and generates a feedback clock, a phase detection unit, which compares phases of the input clock and the feedback clock and generates a phase detection signal, a filter unit, which receives the phase detection signal and generates phase information, generates an update signal when a difference between the numbers of phase detection signals with a first and a second level generated is greater than or equal to a threshold value, and generates the update signal after a lapse of a predetermined time when the difference is less than the threshold value, and a delay line control unit, which sets a delay value of the delay line in response to the update signal and the phase information.

Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.

Abstract: A semiconductor apparatus includes an odd data clock buffer group configured to maintain or shift a phase of a multi-phase source clock signal, and output a first multi-phase clock signal, an even data clock buffer group configured to maintain or shift a phase of the multi-phase source clock signal, and output a second multi-phase clock signal, an odd data output buffer group configured to drive odd data in response to the first multi-phase clock signal and output the driven data to an odd data pad group, and an even data output buffer group configured to drive even data in response to the second multi-phase clock signal and output the driven data to an even data pad group, wherein the phases of clock signals of the first and second multi-phase clock signal are different from each other.

Abstract: A semiconductor device includes a characteristic code storage unit configured to store signal transfer characteristic information input through a given pad and output a control code corresponding to the signal transfer characteristic information, and a characteristic reflection unit configured to reflect the signal transfer characteristic information in an input signal input through the given pad, in response to the control code, and to output the reflected input signal.

Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.

Abstract: A system for transmitting data includes a plurality of data lines configured to transmit the data and a transmitting chip configured to output the data to the data lines and perform a crosstalk prevention operation in response to a data pattern of the data to be transmitted through the data lines and array information of the data lines to prevent crosstalk from occurring in the data lines.

Abstract: A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information.

Abstract: A delay circuit includes a clock delay line, a command delay line, a delay line control block, and a shared shift register block. The clock delay line delays an input clock and generates a delayed clock. The command delay line delays a command signal and generates a delayed command signal. The delay line control block generates a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock. The shared shift register block sets delay amounts of the clock delay line and the command delay line to be substantially the same with each other, in response to the control signal.

Abstract: A reset signal generation apparatus includes a reset signal generation unit and a reset signal expansion unit. The reset signal generation unit enables a reset signal and an enable signal in response to a reset input signal, and disables the reset signal in response to a pulse width extension signal. The reset signal expansion unit generates the pulse width extension signal that is enabled for a predetermined time, in response to the enable signal.

Abstract: A clock generation circuit includes a delay line, which delays an input clock and generates a delayed clock, a delay modeling unit, which delays the delayed clock by a modeled delay value and generates a feedback clock, a phase detection unit, which compares phases of the input clock and the feedback clock and generates a phase detection signal, a filter unit, which receives the phase detection signal and generates phase information, generates an update signal when a difference between the numbers of phase detection signals with a first and a second level generated is greater than or equal to a threshold value, and generates the update signal after a lapse of a predetermined time when the difference is less than the threshold value, and a delay line control unit, which sets a delay value of the delay line in response to the update signal and the phase information.

Abstract: A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage.

Abstract: A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

Abstract: A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.

Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.

Abstract: An output driver includes: a pull-up signal generation unit configured to control a pulse width of first data and output a pull-up pre-drive signal; a pull-down signal generation unit configured to control a pulse width of second data and output a pull-down pre-drive signal; a pull-up pre-driver unit configured to receive the pull-up pre-drive signal and generate a pull-up main drive signal; a pull-down pre-driver unit configured to receive the pull-down pre-drive signal and generate a pull-down main drive signal; a pull-up main driver unit configured to charge an output node according to the pull-up main drive signal; and a pull-down main driver unit configured to discharge the output node according to the pull-down main drive signal.