Patents by Inventor Dae-Hwan Kang
Dae-Hwan Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240092060Abstract: Provided is an unconstrained vibration damping metal sheet with foam pores. The unconstrained vibration damping metal sheet of the present invention comprises: a metal sheet; an organic-inorganic pretreatment layer containing an acrylic resin formed on the metal sheet; and a foam resin layer formed on the pretreatment layer, the foam resin layer containing, based on weight % thereof, a thermoplastic polyvinyl chloride resin: 40-80%, a plasticizer: 5-40%, a foaming agent: 0.1-10%, an oxide-based crosslinker: 1-4%, and spherical silica: 1-10%.Type: ApplicationFiled: November 30, 2021Publication date: March 21, 2024Applicant: POSCO Co., LtdInventors: Jin-Tae Kim, Dae-Gyu Kang, Yang-Ho Choi, Jung-Hwan Lee
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Patent number: 11349074Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.Type: GrantFiled: September 1, 2020Date of Patent: May 31, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hyun Jeong, Jin-Woo Lee, Gwan-Hyeob Koh, Dae-Hwan Kang
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Patent number: 11201192Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.Type: GrantFiled: September 24, 2020Date of Patent: December 14, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hyun Jeong, Gwan-hyeob Koh, Dae-hwan Kang
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Patent number: 11183538Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.Type: GrantFiled: March 31, 2020Date of Patent: November 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-hyun Jeong, Gwan-hyeob Koh, Dae-hwan Kang
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Publication number: 20210013263Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.Type: ApplicationFiled: September 24, 2020Publication date: January 14, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Ji-Hyun JEONG, Gwan-hyeob KOH, Dae-hwan KANG
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Publication number: 20200395542Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.Type: ApplicationFiled: September 1, 2020Publication date: December 17, 2020Inventors: Ji-Hyun JEONG, Jin-Woo LEE, Gwan-Hyeob KOH, Dae-Hwan KANG
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Patent number: 10804466Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.Type: GrantFiled: January 15, 2020Date of Patent: October 13, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hyun Jeong, Jin-Woo Lee, Gwan-Hyeob Koh, Dae-Hwan Kang
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Patent number: 10734450Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.Type: GrantFiled: October 29, 2019Date of Patent: August 4, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyu-Rie Sim, Gwan-Hyeob Koh, Dae-Hwan Kang
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Publication number: 20200227481Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.Type: ApplicationFiled: March 31, 2020Publication date: July 16, 2020Inventors: Ji-hyun JEONG, Gwan-hyeob KOH, Dae-hwan KANG
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Publication number: 20200152869Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Inventors: JI-HYUN JEONG, JIN-WOO LEE, GWAN-HYEOB KOH, DAE-HWAN KANG
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Patent number: 10644069Abstract: A memory device includes a first word line extending in a first direction on a substrate, a first bit line extending in a second direction on the first word line, a first memory cell disposed between the first word line and the first bit line, a second word line extending in the first direction on the first bit line, a second bit line extending in the second direction on the second word line, a second memory cell disposed between the second word line and the second bit line, and a first bit line connection structure connected to the first bit line and the second bit line. The first bit line connection structure includes a first bit line contact connected to the first bit line and a second bit line contact, which is connected to the second bit line and vertically overlaps the first bit line contact.Type: GrantFiled: September 19, 2018Date of Patent: May 5, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Hyun Jeong, Dae-Hwan Kang, Du-Eung Kim, Kwang-Jin Lee
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Patent number: 10636843Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.Type: GrantFiled: February 21, 2019Date of Patent: April 28, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-hyun Jeong, Gwan-hyeob Koh, Dae-hwan Kang
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Patent number: 10615341Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction.Type: GrantFiled: February 15, 2019Date of Patent: April 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang-Woo Lee, Dae-Hwan Kang, Gwan-Hyeob Koh
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Patent number: 10593874Abstract: A variable resistance memory device includes first memory cells and second memory cells. The first memory cells are between first and second conductive lines, and at areas at which the first and second conductive lines overlap. The second memory cells are between the second and third conductive lines, and at areas at which the second and third conductive lines overlap. Each first memory cell includes a first variable resistance pattern and a first selection pattern. Each second memory cell includes a second variable resistance pattern and a second selection pattern. At least one of the second memory cells is shifted from a closest one of the first memory cells.Type: GrantFiled: August 6, 2018Date of Patent: March 17, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Rie Sim, Dae-Hwan Kang, Gwan-Hyeob Koh
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Patent number: 10580979Abstract: A memory device including first conductive lines spaced apart from each other and extending in a first direction; second conductive lines spaced apart from each other and extending in a second direction that is different from the first direction; first memory cells having a structure that includes a selection device layer, a middle electrode layer, a variable resistance layer, and a top electrode layer; and insulating structures arranged alternately with the first memory cells in the second direction under the second conductive lines, wherein the first insulating structures have a top surface that is higher than a top surface of the first top electrode layer, and the second conductive lines have a structure that includes convex and concave portions, the convex portions being connected to the top surface of the top electrode layer and the concave portions accommodating the insulating structures between the convex portions.Type: GrantFiled: August 23, 2018Date of Patent: March 3, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Il-mok Park, Gwan-hyeob Koh, Dae-hwan Kang
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Publication number: 20200066801Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.Type: ApplicationFiled: October 29, 2019Publication date: February 27, 2020Inventors: Kyu-Rie Sim, Gwan-Hyeob Koh, Dae-Hwan Kang
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Patent number: 10566529Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.Type: GrantFiled: January 5, 2018Date of Patent: February 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hyun Jeong, Jin-Woo Lee, Gwan-Hyeob Koh, Dae-Hwan Kang
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Patent number: 10546999Abstract: A variable resistance memory device and a method of manufacturing the same, the device including first conductive lines disposed in a first direction on a substrate, each of the first conductive lines extending in a second direction crossing the first direction, and the first and second directions being parallel to a top surface of the substrate; second conductive lines disposed in the second direction over the first conductive lines, each of the second conductive lines extending in the first direction; a memory unit between the first and second conductive lines, the memory unit being in each area overlapping the first and second conductive lines in a third direction substantially perpendicular to the top surface of the substrate, and the memory unit including a variable resistance pattern; and an insulation layer structure between the first and second conductive lines, the insulation layer structure covering the memory unit and including an air gap in at least a portion of an area overlapping neither the firType: GrantFiled: November 9, 2016Date of Patent: January 28, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Masayuki Terai, Dae-Hwan Kang, Gwan-Hyeob Koh
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Patent number: 10497751Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.Type: GrantFiled: April 27, 2018Date of Patent: December 3, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyu-Rie Sim, Gwan-Hyeob Koh, Dae-Hwan Kang
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Publication number: 20190189692Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.Type: ApplicationFiled: February 21, 2019Publication date: June 20, 2019Inventors: Ji-hyun JEONG, Gwan-hyeob KOH, Dae-hwan KANG