Abstract: A memory device may include a first half memory block, a second half memory block, a row decoder group, and a read/write circuit which may be disposed between the first half memory block and the second half memory block. The read/write circuit may be coupled to the first half memory block and the second half memory block through a first bit line and a second bit line. The row decoder group may be configured to simultaneously select the first half memory block and the second half memory block in response to a single block selection signal.

Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes a pipe gate stack structure in which a portion of a first channel layer is buried. The semiconductor device includes the pipe gate stack structure in which a portion of a second channel layer is buried. The semiconductor device configured to individually control the first and second channel layers.

Abstract: A semiconductor device in accordance with an embodiment may include a cell structure, a source coupling structure, and a source discharge transistor. The cell structure may include alternately stacked first conductive patterns and first interlayer insulating layers enclosing a channel layer. The source coupling structure separated from the cell structure may include alternately stacked second conductive patterns and second interlayer insulating layers. The source discharge transistor may be coupled to the source coupling structure.

Abstract: Disclosed is a semiconductor memory device, including: a slimming structure extended from a cell structure in a direction parallel to the semiconductor substrate, the cell structure having a plurality of cell transistors stacked over a semiconductor substrate; vertical insulating materials extended in a direction crossing the semiconductor substrate and configured to divide the cell structure and the slimming structure into a plurality of memory blocks; contact plugs passing through the vertical insulating materials, respectively, within an area in which the slimming structure is formed; and junctions formed within the semiconductor substrate under the vertical insulating materials, in which the junctions are coupled to the contact plugs, respectively.

Abstract: A semiconductor device in accordance with an embodiment may include a cell structure, a source coupling structure, and a source discharge transistor. The cell structure may include alternately stacked first conductive patterns and first interlayer insulating layers enclosing a channel layer. The source coupling structure separated from the cell structure may include alternately stacked second conductive patterns and second interlayer insulating layers. The source discharge transistor may be coupled to the source coupling structure.

Abstract: A semiconductor device includes a first memory block and a second memory block in a cell region and a first transistor and a second transistor, respectively corresponding to the first and second memory blocks, in a pass transistor region located below the cell region, wherein each of the first and second transistors includes: a first gate electrode coupled to the first memory block and a second gate electrode coupled to the second memory block.

Abstract: A semiconductor memory device to which a Peri Under Cell (PUC) structure is applied is disclosed. The semiconductor memory device includes a word line multilayered structure formed in a cell region, and extending from across the cell region; and a slimming region including a step-shaped pad structure in the word line multilayered structure.

Abstract: A resistor includes a first conductive layer; a second conductive layer protruding from the first conductive layer; a third conductive layer located above and facing the first conductive layer to face the first conductive layer; and at least two contact plugs electrically coupled to the third conductive layer.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device may include a dummy structure formed on a peripheral region of a substrate, and insulating spacers configured to pass through the dummy structure and protrude from an upper surface of the dummy structure. The semiconductor device may include first contact plugs configured to pass through the insulating spacers and protrude from upper surfaces of the insulating spacers.

Abstract: A three-dimensional nonvolatile memory device includes a first vertical channel layer and a second vertical channel layer extending from a substrate, a plurality of memory cells, first selection transistors and second selection transistors spaced apart from each other along the first vertical channel layer and the second vertical channel layer, a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, and a common source line formed over the second vertical channel layer.

Abstract: Disclosed is a semiconductor memory device, including: a slimming structure extended from a cell structure in a direction parallel to the semiconductor substrate, the cell structure having a plurality of cell transistors stacked over a semiconductor substrate; vertical insulating materials extended in a direction crossing the semiconductor substrate and configured to divide the cell structure and the slimming structure into a plurality of memory blocks; contact plugs passing through the vertical insulating materials, respectively, within an area in which the slimming structure is formed; and Junctions formed within the semiconductor substrate under the vertical insulating materials, in which the junctions are coupled to the contact plugs, respectively.

Abstract: A semiconductor device includes a first memory block and a second memory block in a cell region and a first transistor and a second transistor, respectively corresponding to the first and second memory blocks, in a pass transistor region located below the cell region, wherein each of the first and second transistors includes: a first gate electrode coupled to the first memory block and a second gate electrode coupled to the second memory block.

Abstract: A semiconductor memory device to which a Peri Under Cell (PUC) structure is applied is disclosed. The semiconductor memory device includes a word line multilayered structure formed in a cell region, and extending from across the cell region; and a slimming region including a step-shaped pad structure in the word line multilayered structure.

Abstract: A 3D nonvolatile memory device is disclosed. The 3D nonvolatile memory device includes a word line stack in which a plurality of word lines are stacked therein and includes a cell region and a slimming region, and pass transistors located below the word line stack, and electrically coupled to the slimming region. A width of the slimming region is larger than that of the cell region.

Abstract: A 3D nonvolatile memory device is disclosed. The 3D nonvolatile memory device includes a word line stack in which a plurality of word lines are stacked therein and includes a cell region and a slimming region, and pass transistors located below the word line stack, and electrically coupled to the slimming region. A width of the slimming region is larger than that of the cell region.

Abstract: A three-dimensional nonvolatile memory device includes a first vertical channel layer and a second vertical channel layer extending from a substrate, a plurality of memory cells, first selection transistors and second selection transistors spaced apart from each other along the first vertical channel layer and the second vertical channel layer, a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, and a common source line formed over the second vertical channel layer.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device may include a dummy structure formed on a peripheral region of a substrate, and insulating spacers configured to pass through the dummy structure and protrude from an upper surface of the dummy structure. The semiconductor device may include first contact plugs configured to pass through the insulating spacers and protrude from upper surfaces of the insulating spacers.

Abstract: A three-dimensional nonvolatile memory device includes a first vertical channel layer and a second vertical channel layer extending from a substrate, a plurality of memory cells, first selection transistors and second selection transistors spaced apart from each other along the first vertical channel layer and the second vertical channel layer, a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, and a common source line formed over the second vertical channel layer.

Abstract: A semiconductor device may include a first insulating pillar having a substantially Y-shaped cross-sectional structure to define first through third regions, channel pillars formed in the first through third regions, respectively, and second insulating pillars disposed opposite one another across the first through third regions. The semiconductor device may also include third insulating pillars disposed between the second insulating pillars and disposed opposite one another across the first through third regions. The third insulating pillars may extend in a direction intersecting the second insulating pillars.

Abstract: A semiconductor device may include a first insulating pillar having a substantially Y-shaped cross-sectional structure to define first through third regions, channel pillars formed in the first through third regions, respectively, and second insulating pillars disposed opposite one another across the first through third regions. The semiconductor device may also include third insulating pillars disposed between the second insulating pillars and disposed opposite one another across the first through third regions. The third insulating pillars may extend in a direction intersecting the second insulating pillars.