Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a source region and a drain region within a substrate. A gate structure is formed over the substrate and between the source region and the drain region. One or more dielectric layers are formed over the gate structure, and a first inter-level dielectric (ILD) layer is formed over the one or more dielectric layers. The first ILD layer laterally surrounds the gate structure. The first ILD layer is etched to define contact openings and a field plate opening. The contact openings and the field plate opening are filled with a conductive material.

Abstract: The present disclosure, in some embodiments, relates to a transistor device having a field plate. The transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers are arranged over the gate electrode, and a field plate is arranged over the one or more dielectric layers. The field plate extends from a first outermost sidewall that is directly over an upper surface of the gate electrode to a second outermost sidewall that is between the gate electrode and the drain region and that extends to below the upper surface of the gate electrode.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a source region and a drain region within a substrate. A gate structure is formed over the substrate and between the source region and the drain region. One or more dielectric layers are formed over the gate structure, and a first inter-level dielectric (ILD) layer is formed over the one or more dielectric layers. The first ILD layer laterally surrounds the gate structure. The first ILD layer is etched to define contact openings and a field plate opening. The contact openings and the field plate opening are filled with a conductive material.

Abstract: A semiconductor device includes a first a first transistor configured to operate at a first threshold voltage level. The first transistor includes a first gate structure and a first drain terminal electrically coupled to the first gate structure. The semiconductor device also includes a second transistor configured to operate at a second threshold voltage level different from the first threshold voltage level. The second transistor includes a second source terminal and a second gate structure electrically coupled to the first gate structure. The first gate structure and the second gate structure comprise a first component in common, and the second gate structure further includes at least one extra component disposed over the first component. The number of the at least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.

Abstract: The present disclosure, in some embodiments, relates to a transistor device having a field plate. The transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers are arranged over the gate electrode, and a field plate is arranged over the one or more dielectric layers. The field plate extends from a first outermost sidewall that is directly over an upper surface of the gate electrode to a second outermost sidewall that is between the gate electrode and the drain region and that extends to below the upper surface of the gate electrode.

Abstract: The present disclosure relates to a transistor device having a field plate, and a method of formation. In some embodiments, the transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers laterally extend from over the gate electrode to a location between the gate electrode and the drain region. A field plate is located within an inter-level dielectric (ILD) layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the location and vertically extends from the one or more dielectric layers to a top surface of the ILD layer. A conductive contact is arranged over the drain region and is surrounded by the ILD layer. The conductive contact extends to the top surface of the ILD layer.

Abstract: A semiconductor device includes a first a first transistor configured to operate at a first threshold voltage level. The first transistor includes a first gate structure and a first drain terminal electrically coupled to the first gate structure. The semiconductor device also includes a second transistor configured to operate at a second threshold voltage level different from the first threshold voltage level, The second transistor includes a second source terminal and a second gate structure electrically coupled to the first gate structure. The first gate structure and the second gate structure comprise a first component in common, and the second gate structure further includes at least one extra component disposed over the first component. The number of the at least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.

Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first transistor configured to include a first threshold voltage level. The first transistor includes a gate structure. The gate structure includes a first component including a first conductive type. A second transistor configures to include a second threshold voltage level different from the first threshold voltage level. The second transistor includes a gate structure. The gate structure includes a second component including the first conductive type. At least one extra component is disposed over the second component. The least one extra component includes a second conductive type opposite to the first conductive type. The first transistor and the second transistor are coupled such that the number of the least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.

Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first transistor configured to include a first threshold voltage level. The first transistor includes a gate structure. The gate structure includes a first component including a first conductive type. A second transistor configures to include a second threshold voltage level different from the first threshold voltage level. The second transistor includes a gate structure. The gate structure includes a second component including the first conductive type. At least one extra component is disposed over the second component. The least one extra component includes a second conductive type opposite to the first conductive type. The first transistor and the second transistor are coupled such that the number of the least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.

Abstract: The present disclosure relates to a transistor device having a field plate, and a method of formation. In some embodiments, the transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers laterally extend from over the gate electrode to a location between the gate electrode and the drain region. A field plate is located within an inter-level dielectric (ILD) layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the location and vertically extends from the one or more dielectric layers to a top surface of the ILD layer. A conductive contact is arranged over the drain region and is surrounded by the ILD layer. The conductive contact extends to the top surface of the ILD layer.

Abstract: The present disclosure relates to a high voltage transistor device having a field plate, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to a drift region arranged between the gate electrode and the drain region. A field plate is located within a first inter-level dielectric layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the drift region and vertically extends from the dielectric layer to a top surface of the first ILD layer. A plurality of metal contacts, having a same material as the field plate, vertically extend from a bottom surface of the first ILD layer to a top surface of the first ILD layer.

Abstract: The present disclosure relates to a high voltage transistor device having a field plate, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to a drift region arranged between the gate electrode and the drain region. A field plate is located within a first inter-level dielectric layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the drift region and vertically extends from the dielectric layer to a top surface of the first ILD layer. A plurality of metal contacts, having a same material as the field plate, vertically extend from a bottom surface of the first ILD layer to a top surface of the first ILD layer.

Abstract: A method comprising providing a first substrate and forming a first sacrificial layer over the first substrate, the first sacrificial layer comprising a curved surface portion, and forming a curved micromirror by depositing a reflective material over at the curved surface portion.

Abstract: An electrostatic discharge (ESD) protection circuit includes at least one bipolar transistor. At least one isolation structure is disposed in a substrate. The at least one isolation structure is configured to electrically isolate two terminals of the at least one bipolar transistor. At least one diode is electrically coupled with the at least one bipolar transistor, wherein a junction interface of the at least one diode is disposed adjacent the at least one isolation structure.

Abstract: An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.

Abstract: An electrostatic discharge (ESD) protection circuit includes at least one bipolar transistor. At least one isolation structure is disposed in a substrate. The at least one isolation structure is configured to electrically isolate two terminals of the at least one bipolar transistor. At least one diode is electrically coupled with the at least one bipolar transistor, wherein a junction interface of the at least one diode is disposed adjacent the at least one isolation structure.

Abstract: A high-voltage Schottky diode including a deep P-well having a first width is formed on the semiconductor substrate. A doped P-well is disposed over the deep P-well and has a second width that is less than the width of the deep P-well. An M-type guard ring is formed around the upper surface of the second doped well, A Schottky metal is disposed on an upper surface of the second doped well and the N-type guard ring.

Abstract: A high-voltage Schottky diode including a deep P-well having a first width is fanned on the semiconductor substrate. A doped P-well is disposed over the deep P-well and has a second width that is less than the width of the deep P-well. An M-type guard ring is formed around the upper surface of the second doped well, A Schottky metal is disposed on an upper surface of the second doped well and the N-type guard ring.

Abstract: An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.

Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms.