Abstract: An imaging device having an optical system according to an embodiment includes an imager, an information acquirer, and a processor. The imager captures an image via the optical system. The information acquirer acquires peculiar information transmitted from a peculiar information transmitter. The processor processes for associating the peculiar information and the image when the peculiar information transmitter is located within an imaging range of the optical system.

Abstract: An imaging device having an optical system according to an embodiment includes an imager, an information acquirer, and a processor. The imager captures an image via the optical system. The information acquirer acquires peculiar information transmitted from a peculiar information transmitter. The processor processes for associating the peculiar information and the image when the peculiar information transmitter is located within an imaging range of the optical system.

Abstract: Circuit protecting against electrostatic discharge (ESD) includes a bias circuit connected in between a first power terminal and a second power terminal. The bias circuit includes a resistor circuit and a diode circuit. The diode circuit comprises multiple diodes connected in series. During ESD protective operation, the bias circuit supplies a bias terminal with a clamping voltage that is higher than the ordinary power supply voltage. The bias terminal is connected to a driver circuit including at least one inverter circuit. Depending on the voltage of the bias terminal and the voltage of the first power terminal, the driver circuit controls the conduction state of a shunt transistor by supplying a voltage to the gate electrode of the shunt transistor.

Abstract: According to one embodiment, a memory cell is configured using a field effect transistor and includes n anti-fuse elements, one ends of which are connected in common. A program voltage selection circuit selects, out of the n anti-fuse elements, an anti-fuse element to which a program voltage is applied. A sense amplifier is provided for the each memory cell and determines, based on data stored in the n anti-fuse elements, three or more values of readout levels.

Abstract: According to one embodiment, a memory cell is configured using a field effect transistor and includes n anti-fuse elements, one ends of which are connected in common. A program voltage selection circuit selects, out of the n anti-fuse elements, an anti-fuse element to which a program voltage is applied. A sense amplifier is provided for the each memory cell and determines, based on data stored in the n anti-fuse elements, three or more values of readout levels.

Abstract: A memory cell array is configured as an arrangement of memory cells. A first voltage generating circuit is configured to, during a write operation on the memory cells, generate and supply to the memory cell array a first voltage from a constant voltage, and to, during a read operation on the memory cells, generate and supply to the memory cell array a second voltage from a power supply voltage. A second voltage generating circuit is configured to generate the constant voltage. A selector circuit is configured to, during the write operation, drive the second voltage generating circuit to supply to the first voltage generating circuit the constant voltage, and to, during the read operation, stop the second voltage generating circuit and supply to the first voltage generating circuit the power supply voltage.

Abstract: A semiconductor memory device includes n stages of memory cell units, sense amplifier units, and shift registers. N units of the shift registers are connected to one another on the left end sides. The signal processing units and the reversed signal processing units are disposed adjacent to one another in each of the n units of the shift registers. The signal processing units located on the odd-numbered positions counted from the input end side are connected to one another. The reversed signal processing units located on the even-numbered positions counted from the input end side are connected to one another. The signal processing units located on the end opposite to the input end side are connected to the reversed signal processing units located on the end opposite to the input end side. Each of the signal processing units includes the logic circuit unit and the flip-flop while each of the reversed signal processing units includes the reversed logic circuit unit and the reversed flip-flop.

Abstract: A nonvolatile semiconductor memory device includes a memory cell, a precharge control circuit, a power supply circuit, a bit line driver, a word line driver, a first multiplexer, and a second multiplexer. The memory cell includes an anti-fuse storage element and a selection transistor. Before data are written into the anti-fuse storage element of the memory cell, the anti-fuse storage element is set up in a precharged state by the precharge control circuit, the bit line driver, the word line driver, the first multiplexer, and the second multiplexer.

Abstract: A memory cell array is configured as an arrangement of memory cells. A first voltage generating circuit is configured to, during a write operation on the memory cells, generate and supply to the memory cell array a first voltage from a constant voltage, and to, during a read operation on the memory cells, generate and supply to the memory cell array a second voltage from a power supply voltage. A second voltage generating circuit is configured to generate the constant voltage. A selector circuit is configured to, during the write operation, drive the second voltage generating circuit to supply to the first voltage generating circuit the constant voltage, and to, during the read operation, stop the second voltage generating circuit and supply to the first voltage generating circuit the power supply voltage.

Abstract: A semiconductor memory device includes n stages of memory cell units, sense amplifier units, and shift registers. N units of the shift registers are connected to one another on the left end sides. The signal processing units and the reversed signal processing units are disposed adjacent to one another in each of the n units of the shift registers. The signal processing units located on the odd-numbered positions counted from the input end side are connected to one another. The reversed signal processing units located on the even-numbered positions counted from the input end side are connected to one another. The signal processing units located on the end opposite to the input end side are connected to the reversed signal processing units located on the end opposite to the input end side. Each of the signal processing units includes the logic circuit unit and the flip-flop while each of the reversed signal processing units includes the reversed logic circuit unit and the reversed flip-flop.

Abstract: A nonvolatile semiconductor memory device includes a memory cell, a precharge control circuit, a power supply circuit, a bit line driver, a word line driver, a first multiplexer, and a second multiplexer. The memory cell includes an anti-fuse storage element and a selection transistor. Before data are written into the anti-fuse storage element of the memory cell, the anti-fuse storage element is set up in a precharged state by the precharge control circuit, the bit line driver, the word line driver, the first multiplexer, and the second multiplexer.