Patents by Inventor Daigo Ito

Daigo Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10685983
    Abstract: To provide a semiconductor device capable of retaining data for a long time. The semiconductor device includes a first transistor, an insulator covering the first transistor, and a second transistor over the insulator. The first transistor includes a first gate electrode, a second gate electrode overlapping with the first gate electrode, and a semiconductor between the first gate electrode and the second gate electrode. The first gate electrode is electrically connected to one of a source and a drain of the second transistor.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: June 16, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daigo Ito, Yutaka Okazaki, Takahisa Ishiyama
  • Publication number: 20200185528
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes an oxide; a first conductor and a second conductor over the oxide; a third conductor over the oxide; a first insulator provided between the oxide and the third conductor and covering a side surface of the third conductor; a second insulator over the third conductor and the first insulator; a third insulator positioned over the first conductor and at a side surface of the second insulator; a fourth insulator positioned over the second conductor and at a side surface of the second insulator; a fourth conductor being in contact with a top surface and a side surface of the third insulator and electrically connected to the first conductor; and a fifth conductor being in contact with a top surface and a side surface of the fourth insulator and electrically connected to the second conductor.
    Type: Application
    Filed: July 26, 2018
    Publication date: June 11, 2020
    Inventors: Shunpei YAMAZAKI, Daisuke MATSUBAYASHI, Ryota HODO, Daigo ITO, Hiroaki HONDA, Satoru OKAMOTO
  • Publication number: 20200153039
    Abstract: A solid-state rechargeable battery includes a pair of electrode layers and a solid electrolyte layer interposed between the pair of electrode layers. The pair of electrode layers each includes a phosphate having an olivine crystal structure. The phosphate contains a transition metal and lithium.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Applicant: TAIYO YUDEN CO. LTD.
    Inventor: Daigo ITO
  • Publication number: 20200127137
    Abstract: To provide a semiconductor device in which a large current can flow. To provide a semiconductor device which can be driven stably at a high driving voltage. The semiconductor device includes a semiconductor layer, a first electrode and a second electrode electrically connected to the semiconductor layer and apart from each other in a region overlapping with the semiconductor layer, a first gate electrode and a second gate electrode with the semiconductor layer therebetween, a first gate insulating layer between the semiconductor layer and the first gate electrode, and a second gate insulating layer between the semiconductor layer and the second gate electrode. The first gate electrode overlaps with part of the first electrode, the semiconductor layer, and part of the second electrode. The second gate electrode overlaps with the semiconductor layer and part of the first electrode, and does not overlap with the second electrode.
    Type: Application
    Filed: November 25, 2019
    Publication date: April 23, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Yoshiyuki KOBAYASHI, Daisuke MATSUBAYASHI, Akihisa SHIMOMURA, Daigo ITO
  • Patent number: 10615187
    Abstract: A highly reliable semiconductor device capable of retaining data for a long period is provided. The transistor includes a first gate electrode, a first gate insulator over the first gate electrode, a first oxide and a second oxide over the first gate insulator, a first conductor over the first oxide, a second conductor over the second oxide, a third oxide covering the first gate insulator, the first oxide, the first conductor, the second oxide, and the second conductor, a second gate insulator over the third oxide, and a second gate electrode over the second gate insulator. An end portion of the second gate electrode is positioned between an end portion of the first conductor and an end portion of the second conductor in a channel length direction.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: April 7, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinpei Matsuda, Daigo Ito, Daisuke Matsubayashi, Yasutaka Suzuki, Etsuko Kamata, Yutaka Shionoiri, Shuhei Nagatsuka
  • Publication number: 20200106088
    Abstract: An all solid battery includes: a first electrode layer that includes a positive electrode active material and a Li—La—Ti—O-based oxide; a second electrode layer that includes a positive electrode active material and a Li—La—Ti—O-based oxide; and a solid electrolyte layer that includes an oxide-based solid electrolyte and is sandwiched by the first electrode layer and the second electrode layer.
    Type: Application
    Filed: September 16, 2019
    Publication date: April 2, 2020
    Inventors: Daigo ITO, Takato SATOH, Sachie TOMIZAWA, Chie KAWAMURA
  • Publication number: 20200106129
    Abstract: An all solid battery includes: a solid electrolyte layer including solid electrolyte; a first electrode layer that is formed on a first main face of the solid electrolyte layer and includes an active material; and a second electrode layer that is formed on a second main face of the solid electrolyte layer and includes an active material, wherein the solid electrolyte layer includes polymer solid electrolyte including lithium salt, in a clearance of a sintered compact of phosphoric acid salt-based solid electrolyte.
    Type: Application
    Filed: September 16, 2019
    Publication date: April 2, 2020
    Inventors: Takato SATOH, Daigo ITO, Sachie TOMIZAWA, Chie KAWAMURA
  • Publication number: 20200105942
    Abstract: The semiconductor device includes a first insulating layer; a first oxide insulating layer over the first insulating layer; an oxide semiconductor layer over the first oxide insulating layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; a second oxide insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; a gate insulating layer over the second oxide insulating layer; a gate electrode layer over the gate insulating layer; a second insulating layer over the first insulating layer the source electrode layer, the drain electrode layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer, and a third insulating layer over the first insulating layer, the source electrode layer, the drain electrode layer, and the second insulating layer.
    Type: Application
    Filed: December 4, 2019
    Publication date: April 2, 2020
    Inventors: Daigo ITO, Takahisa ISHIYAMA, Katsuaki TOCHIBAYASHI, Kazuya HANAOKA
  • Publication number: 20200091522
    Abstract: An all solid battery includes: a solid electrolyte layer of which a main component is phosphoric acid salt-based solid electrolyte; a positive electrode layer that is formed on a first main face of the solid electrolyte layer; and a negative electrode layer that is formed on a second main face of the solid electrolyte layer, wherein the positive electrode layer includes a positive electrode active material and a solid electrolyte, wherein a discharge capacity of the solid electrolyte of the positive electrode layer is 20% to 50% on a presumption that a discharge capacity of the positive electrode active material is 100%.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 19, 2020
    Inventors: Daigo ITO, Takato SATOH, Sachie TOMIZAWA, Chie KAWAMURA
  • Publication number: 20200083567
    Abstract: A manufacturing method of an all solid battery includes: preparing a multilayer structure in which first coated electric collector paste including Pd, first coated electrode paste including carbon, a green sheet including phosphoric acid salt-based solid electrolyte grains, second coated electrode paste including carbon and second coated electric collector paste including Pd are stacked in this order; and firing the multilayer structure within an oxygen partial pressure range from 5×10?22 atm or more and 2×10?13 atm or less.
    Type: Application
    Filed: September 4, 2019
    Publication date: March 12, 2020
    Inventors: Sachie TOMIZAWA, Daigo ITO, Chie KAWAMURA, Takato SATOH
  • Publication number: 20200083563
    Abstract: An all solid battery includes: a solid electrolyte layer including phosphoric acid salt-based solid electrolyte; a first electrode that is formed on a first main face of the solid electrolyte layer; and a second electrode that is formed on a second main face of the solid electrolyte layer, wherein a D50% grain diameter of crystal grains of the phosphoric acid salt-based solid electrolyte is 0.5 ?m or less, wherein a D90% grain diameter of the crystal grains is 3 ?m or less.
    Type: Application
    Filed: September 4, 2019
    Publication date: March 12, 2020
    Inventors: Chie KAWAMURA, Sachie TOMIZAWA, Daigo ITO, Takato SATOH
  • Patent number: 10505051
    Abstract: The semiconductor device includes a first insulating layer; a first oxide insulating layer over the first insulating layer; an oxide semiconductor layer over the first oxide insulating layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; a second oxide insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; a gate insulating layer over the second oxide insulating layer; a gate electrode layer over the gate insulating layer; a second insulating layer over the first insulating layer, the source electrode layer, the drain electrode layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer; and a third insulating layer over the first insulating layer, the source electrode layer, the drain electrode layer, and the second insulating layer.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: December 10, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daigo Ito, Takahisa Ishiyama, Katsuaki Tochibayashi, Kazuya Hanaoka
  • Publication number: 20190305369
    Abstract: An all solid battery includes: a solid electrolyte layer; a first electrode layer that is formed on a first main face of the solid electrolyte layer; a first electric collector layer that is formed on a face of the first electrode layer, the face being opposite to the first main face; a second electrode layer that is formed on a second main face of the solid electrolyte layer; and a second electric collector layer that is formed on a face of the second electrolyte layer, the face being opposite to the second main face, wherein at least one of the first electric collector layer and the second electric collector layer includes Pd and board-shaped graphite carbon, wherein a volume ratio of Pd and the board-shaped graphite carbon in the at least one of the first electric collector layer and the second electric collector layer is 20:80 to 80:20.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 3, 2019
    Inventors: Daigo ITO, Takato SATOH, Sachie TOMIZAWA, Chie KAWAMURA
  • Publication number: 20190131654
    Abstract: An all solid battery includes: a solid electrolyte layer; a positive electrode layer provided on a first face of the solid electrolyte layer, a part of the positive electrode layer extending to a first edge portion of the solid electrolyte layer; a first margin layer that is provided on an area of the solid electrolyte layer where the positive electrode is not provided; a negative electrolyte layer provided on a second face of the solid electrolyte layer, a part of the negative electrolyte layer extending to a second edge portion of the solid electrolyte layer; a second margin layer that is provided on an area of the second face of the solid electrolyte layer where the negative electrolyte layer is not provided; wherein a main component of the first margin layer and the second margin layer is solid electrolyte of which ionic conductivity is lower than that of the solid electrolyte layer.
    Type: Application
    Filed: October 31, 2018
    Publication date: May 2, 2019
    Inventors: Daigo ITO, Takato SATOH, Sachie TOMIZAWA, Chie KAWAMURA
  • Publication number: 20190131616
    Abstract: An all solid battery includes: a solid electrolyte layer including an oxide-based electrolyte; a first electrode layer that is formed on a first face of the solid electrolyte layer and includes a ceramic grain; and a second electrode layer that is formed on a second face of the solid electrolyte layer and includes a ceramic grain, wherein at least one of the first electrode layer and the second electrode layer includes a micro particle carbon and a board-shaped carbon.
    Type: Application
    Filed: November 1, 2018
    Publication date: May 2, 2019
    Inventors: Sachie TOMIZAWA, Daigo ITO
  • Patent number: 10263117
    Abstract: A semiconductor device having favorable electric characteristics is provided. An oxide semiconductor layer includes first and second regions apart from each other, a third region which is between the first and second regions and overlaps with a gate electrode layer with a gate insulating film provided therebetween, a fourth region between the first and third regions, and a fifth region between the second and third regions. A source electrode layer includes first and second conductive layers. A drain electrode layer includes third and fourth conductive layers. The first conductive layer is formed only over the first region. The second conductive layer is in contact with an insulating layer, the first conductive layer, and the first region. The third conductive layer is formed only over the second region. The fourth conductive layer is in contact with the insulating layer, the third conductive layer, and the second region.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: April 16, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daigo Ito, Kazuya Hanaoka
  • Patent number: 10249905
    Abstract: An all-solid-state secondary battery, including: a solid electrolyte layer; a positive electrode layer including a positive electrode active material layer and a first current collector layer; a negative electrode layer including a second current collector layer, the positive electrode layer and the negative electrode layer sandwiching the solid electrolyte layer; and external electrodes connected respectively to the first current collector layer and the second current collector layer, wherein the positive electrode active material layer is formed of an olivine-type active material, wherein the solid electrolyte layer is formed of a phosphate having a NASICON-type structure, and wherein the solid electrolyte layer contains particulate precipitate having an olivine-type crystal structure that includes a same element as an element forming the positive electrode active material layer.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: April 2, 2019
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Daigo Ito, Masaki Mochigi, Masataka Tomita, Toshimasa Suzuki
  • Patent number: 10141452
    Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: November 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daigo Ito, Daisuke Matsubayashi, Masaharu Nagai, Yoshiaki Yamamoto, Takashi Hamada, Yutaka Okazaki, Shinya Sasagawa, Motomu Kurata, Naoto Yamade
  • Publication number: 20180197997
    Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer.
    Type: Application
    Filed: January 8, 2018
    Publication date: July 12, 2018
    Inventors: Daigo ITO, Daisuke Matsubayashi, Masaharu Nagai, Yoshiaki Yamamoto, Takashi Hamada, Yutaka Okazaki, Shinya Sasagawa, Motomu Kurata, Naoto Yamade
  • Patent number: 10020322
    Abstract: A highly reliable semiconductor device which includes an oxide semiconductor is provided. Alternatively, a transistor having normally-off characteristics which includes an oxide semiconductor is provided. The transistor includes a first conductor, a first insulator, a second insulator, a third insulator, a first oxide, an oxide semiconductor, a second conductor, a second oxide, a fourth insulator, a third conductor, a fourth conductor, a fifth insulator, and a sixth insulator. The second conductor is separated from the sixth insulator by the second oxide. The third conductor and the fourth conductor are separated from the sixth insulator by the fifth insulator. The second oxide has a function of suppressing permeation of oxygen as long as oxygen contained in the sixth insulator is sufficiently supplied to the oxide semiconductor through the second oxide. The fifth insulator has a barrier property against oxygen.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: July 10, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daigo Ito, Takahisa Ishiyama, Katsuaki Tochibayashi, Yoshinori Ando, Yasutaka Suzuki, Mitsuhiro Ichijo, Toshiya Endo, Shunpei Yamazaki